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burrbullburrbull
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repr-u32
1 parent 0ffa14c commit 26f646d

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5 files changed

+29
-29
lines changed

5 files changed

+29
-29
lines changed

‎src/dma/mod.rs

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -301,7 +301,7 @@ impl Not for CurrentBuffer {
301301

302302
/// Structure to get or set common interrupts setup
303303
#[enumflags2::bitflags]
304-
#[repr(u8)]
304+
#[repr(u32)]
305305
#[derive(Clone, Copy, PartialEq, Eq, Debug, Hash)]
306306
pub enum DmaEvent {
307307
DirectModeError = 1 << 1,
@@ -331,7 +331,7 @@ impl DmaEventExt for BitFlags<DmaEvent> {
331331

332332
/// Structure returned by Stream or Transfer flags() method.
333333
#[enumflags2::bitflags]
334-
#[repr(u8)]
334+
#[repr(u32)]
335335
#[derive(Clone, Copy, PartialEq, Eq, Debug, Hash)]
336336
pub enum DmaFlag {
337337
FifoError = 1 << 0,
@@ -600,7 +600,7 @@ where
600600

601601
#[inline(always)]
602602
fn events(&self) -> BitFlags<DmaEvent> {
603-
BitFlags::from_bits_truncate(unsafe { Self::st() }.cr.read().bits() as u8)
603+
BitFlags::from_bits_truncate(unsafe { Self::st() }.cr.read().bits())
604604
}
605605

606606
#[inline(always)]
@@ -679,10 +679,10 @@ where
679679
w.bits({
680680
let mut bits = r.bits();
681681
if let Some(d) = disable {
682-
bits &= !(d.bits() as u32)
682+
bits &= !d.bits()
683683
}
684684
if let Some(e) = enable {
685-
bits |= e.bits() as u32;
685+
bits |= e.bits();
686686
}
687687
bits
688688
})
@@ -704,7 +704,7 @@ macro_rules! dma_stream {
704704
#[inline(always)]
705705
fn clear_flags(&mut self, flags: impl Into<BitFlags<DmaFlag>>) {
706706
let dma = unsafe { &*I::ptr() };
707-
dma.$ifcr.write(|w| unsafe { w.bits((flags.into().bits() as u32) << $isr_shift) });
707+
dma.$ifcr.write(|w| unsafe { w.bits(flags.into().bits() << $isr_shift) });
708708
}
709709
}
710710

@@ -717,7 +717,7 @@ macro_rules! dma_stream {
717717
//NOTE(unsafe) Atomic read with no side effects
718718
let dma = unsafe { &*I::ptr() };
719719
BitFlags::from_bits_truncate(
720-
((dma.$isr.read().bits() >> $isr_shift)) as u8
720+
((dma.$isr.read().bits() >> $isr_shift))
721721
)
722722
}
723723
}

‎src/serial.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ pub enum Error {
5454
#[enumflags2::bitflags]
5555
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
5656
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
57-
#[repr(u16)]
57+
#[repr(u32)]
5858
pub enum Event {
5959
/// IDLE interrupt enable
6060
Idle = 1 << 4,
@@ -72,7 +72,7 @@ pub enum Event {
7272
#[enumflags2::bitflags]
7373
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7474
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
75-
#[repr(u16)]
75+
#[repr(u32)]
7676
pub enum Flag {
7777
/// Parity error
7878
ParityError = 1 << 0,
@@ -100,7 +100,7 @@ pub enum Flag {
100100
#[enumflags2::bitflags]
101101
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
102102
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
103-
#[repr(u16)]
103+
#[repr(u32)]
104104
pub enum CFlag {
105105
/// Read data register not empty
106106
RxNotEmpty = 1 << 5,

‎src/serial/uart_impls.rs

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -282,12 +282,11 @@ macro_rules! uartCommon {
282282
}
283283

284284
fn flags(&self) -> BitFlags<Flag> {
285-
BitFlags::from_bits_truncate(self.sr.read().bits() as u16)
285+
BitFlags::from_bits_truncate(self.sr.read().bits())
286286
}
287287

288288
fn clear_flags(&self, flags: BitFlags<CFlag>) {
289-
self.sr
290-
.write(|w| unsafe { w.bits(0xffff & !(flags.bits() as u32)) });
289+
self.sr.write(|w| unsafe { w.bits(0xffff & !flags.bits()) });
291290
}
292291

293292
fn clear_idle_interrupt(&self) {

‎src/spi.rs

Lines changed: 14 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ use core::ops::{Deref, DerefMut};
44
use crate::dma::traits::{DMASet, PeriAddress};
55
use crate::dma::{MemoryToPeripheral, PeripheralToMemory};
66
use crate::gpio::{self, NoPin};
7-
use crate::{pac, ClearFlags, ReadFlags};
7+
use crate::{pac, ReadFlags};
88

99
/// Clock polarity
1010
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
@@ -67,7 +67,7 @@ pub type NoMosi = NoPin;
6767
#[enumflags2::bitflags]
6868
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
6969
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
70-
#[repr(u8)]
70+
#[repr(u32)]
7171
pub enum Event {
7272
/// An error occurred.
7373
///
@@ -90,7 +90,7 @@ pub enum Event {
9090
#[enumflags2::bitflags]
9191
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9292
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
93-
#[repr(u16)]
93+
#[repr(u32)]
9494
pub enum Flag {
9595
/// Receive buffer not empty
9696
RxNotEmpty = 1 << 0,
@@ -112,7 +112,7 @@ pub enum Flag {
112112
#[enumflags2::bitflags]
113113
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
114114
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
115-
#[repr(u16)]
115+
#[repr(u32)]
116116
pub enum CFlag {
117117
/// CRC error flag
118118
CrcError = 1 << 4,
@@ -788,7 +788,7 @@ impl<SPI: Instance> Inner<SPI> {
788788
Error::ModeFault.into()
789789
} else if flags.contains(Flag::CrcError) {
790790
// Clear the CRCERR bit
791-
self.clear_flags(CFlag::CrcError);
791+
self.spi.sr.modify(|_r, w| w.crcerr().clear_bit());
792792
Error::Crc.into()
793793
} else if flags.contains(Flag::TxEmpty) {
794794
self.write_data_reg(byte);
@@ -802,10 +802,10 @@ impl<SPI: Instance> Inner<SPI> {
802802
w.bits({
803803
let mut bits = r.bits();
804804
if let Some(d) = disable {
805-
bits &= !(d.bits() as u32)
805+
bits &= !d.bits();
806806
}
807807
if let Some(e) = enable {
808-
bits |= e.bits() as u32;
808+
bits |= e.bits();
809809
}
810810
bits
811811
})
@@ -831,18 +831,19 @@ impl<SPI: Instance> crate::Listen for Inner<SPI> {
831831

832832
impl<SPI: Instance> crate::ClearFlags for Inner<SPI> {
833833
type Flag = CFlag;
834-
fn clear_flags(&mut self, event: impl Into<BitFlags<Self::Flag>>) {
835-
// TODO: check
836-
self.spi
837-
.sr
838-
.write(|w| unsafe { w.bits(0xffff & !(event.into().bits() as u32)) });
834+
fn clear_flags(&mut self, flags: impl Into<BitFlags<Self::Flag>>) {
835+
if flags.into().contains(CFlag::CrcError) {
836+
self.spi
837+
.sr
838+
.write(|w| unsafe { w.bits(0xffff).crcerr().clear_bit() })
839+
}
839840
}
840841
}
841842

842843
impl<SPI: Instance> crate::ReadFlags for Inner<SPI> {
843844
type Flag = Flag;
844845
fn flags(&self) -> BitFlags<Self::Flag> {
845-
BitFlags::from_bits_truncate(self.spi.sr.read().bits() as u16)
846+
BitFlags::from_bits_truncate(self.spi.sr.read().bits())
846847
}
847848
}
848849

‎src/timer.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -90,7 +90,7 @@ pub enum SysEvent {
9090

9191
/// TIM interrupt events
9292
#[enumflags2::bitflags]
93-
#[repr(u8)]
93+
#[repr(u32)]
9494
#[derive(Clone, Copy, PartialEq, Eq, Debug, Hash)]
9595
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9696
pub enum Event {
@@ -114,7 +114,7 @@ pub enum Event {
114114

115115
/// TIM status flags
116116
#[enumflags2::bitflags]
117-
#[repr(u16)]
117+
#[repr(u32)]
118118
#[derive(Clone, Copy, PartialEq, Eq, Debug, Hash)]
119119
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
120120
pub enum Flag {
@@ -450,7 +450,7 @@ macro_rules! hal {
450450
}
451451
#[inline(always)]
452452
fn get_interrupt_flag(&self) -> BitFlags<Flag> {
453-
BitFlags::from_bits_truncate(self.sr.read().bits() as u16)
453+
BitFlags::from_bits_truncate(self.sr.read().bits())
454454
}
455455
#[inline(always)]
456456
fn read_count(&self) -> Self::Width {

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