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src/spi.rs

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -704,34 +704,34 @@ impl<SPI: Instance> Inner<SPI> {
704704
/// can be written to the SPI.
705705
#[inline]
706706
pub fn is_tx_empty(&self) -> bool {
707-
self.flags().contains(Flag::TxEmpty)
707+
self.spi.sr.read().txe().bit_is_set()
708708
}
709709

710710
/// Return `true` if the RXNE flag is set, i.e. new data has been received
711711
/// and can be read from the SPI.
712712
#[inline]
713713
pub fn is_rx_not_empty(&self) -> bool {
714-
self.flags().contains(Flag::RxNotEmpty)
714+
self.spi.sr.read().rxne().bit_is_set()
715715
}
716716

717717
/// Return `true` if the MODF flag is set, i.e. the SPI has experienced a
718718
/// Master Mode Fault. (see chapter 28.3.10 of the STM32F4 Reference Manual)
719719
#[inline]
720720
pub fn is_modf(&self) -> bool {
721-
self.flags().contains(Flag::ModeFault)
721+
self.spi.sr.read().modf().bit_is_set()
722722
}
723723

724724
/// Returns true if the transfer is in progress
725725
#[inline]
726726
pub fn is_busy(&self) -> bool {
727-
self.flags().contains(Flag::Busy)
727+
self.spi.sr.read().bsy().bit_is_set()
728728
}
729729

730730
/// Return `true` if the OVR flag is set, i.e. new data has been received
731731
/// while the receive data register was already filled.
732732
#[inline]
733733
pub fn is_overrun(&self) -> bool {
734-
self.flags().contains(Flag::Overrun)
734+
self.spi.sr.read().ovr().bit_is_set()
735735
}
736736

737737
#[inline]
@@ -759,15 +759,15 @@ impl<SPI: Instance> Inner<SPI> {
759759

760760
#[inline(always)]
761761
fn check_read<W: FrameSize>(&mut self) -> nb::Result<W, Error> {
762-
let flags = self.flags();
762+
let sr = self.spi.sr.read();
763763

764-
Err(if flags.contains(Flag::Overrun) {
764+
Err(if sr.ovr().bit_is_set() {
765765
Error::Overrun.into()
766-
} else if flags.contains(Flag::ModeFault) {
766+
} else if sr.modf().bit_is_set() {
767767
Error::ModeFault.into()
768-
} else if flags.contains(Flag::CrcError) {
768+
} else if sr.crcerr().bit_is_set() {
769769
Error::Crc.into()
770-
} else if flags.contains(Flag::RxNotEmpty) {
770+
} else if sr.rxne().bit_is_set() {
771771
return Ok(self.read_data_reg());
772772
} else {
773773
nb::Error::WouldBlock
@@ -776,21 +776,21 @@ impl<SPI: Instance> Inner<SPI> {
776776

777777
#[inline(always)]
778778
fn check_send<W: FrameSize>(&mut self, byte: W) -> nb::Result<(), Error> {
779-
let flags = self.flags();
779+
let sr = self.spi.sr.read();
780780

781-
Err(if flags.contains(Flag::Overrun) {
781+
Err(if sr.ovr().bit_is_set() {
782782
// Read from the DR to clear the OVR bit
783783
let _ = self.spi.dr.read();
784784
Error::Overrun.into()
785-
} else if flags.contains(Flag::ModeFault) {
785+
} else if sr.modf().bit_is_set() {
786786
// Write to CR1 to clear MODF
787787
self.spi.cr1.modify(|_r, w| w);
788788
Error::ModeFault.into()
789-
} else if flags.contains(Flag::CrcError) {
789+
} else if sr.crcerr().bit_is_set() {
790790
// Clear the CRCERR bit
791791
self.spi.sr.modify(|_r, w| w.crcerr().clear_bit());
792792
Error::Crc.into()
793-
} else if flags.contains(Flag::TxEmpty) {
793+
} else if sr.txe().bit_is_set() {
794794
self.write_data_reg(byte);
795795
return Ok(());
796796
} else {

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