From 0460537953d623391366bfb16678cca967fa94da Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fabian=20Vi=C3=B6l?= Date: Thu, 24 Feb 2022 20:41:22 +0100 Subject: [PATCH 1/7] Ideas --- src/timer.rs | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/timer.rs b/src/timer.rs index 6560e8244..5e24044cb 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -102,6 +102,8 @@ pub struct Timer { pub enum Event { /// Timer timed out / count down ended Update, + // CounterUnderflow, + // CounterOverflow, } impl Timer @@ -109,6 +111,7 @@ where TIM: Instance, { /// Configures a TIM peripheral as a periodic count down timer + // TODO: CHange clocks to be a global variable pub fn new(tim: TIM, clocks: Clocks, apb: &mut ::Bus) -> Self { TIM::enable(apb); TIM::reset(apb); @@ -344,6 +347,9 @@ where /// based on [`crate::pac::tim6::RegisterBlock`]. /// /// This is not meant to be used outside of this crate. +// TODO: Maybe use transmute to create a real basic common register block +// (e.g. pac::tim6::ReigsterBlock), as all blocks should be compatible to +// each other ... (hopefully). pub trait CommonRegisterBlock: crate::private::Sealed { #[doc(hidden)] fn set_cr1_cen(&mut self, enable: bool); @@ -582,3 +588,7 @@ cfg_if::cfg_if! { timer_var_clock!(1); } } + +fn test(tim: pac::TIM16) { + let tim6: *const pac::tim6::RegisterBlock = unsafe {core::mem::transmute(pac::TIM16::ptr())}; +} From dd9d667d09a0b0a82c30e78395f3681cff4e78f0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fabian=20Vi=C3=B6l?= Date: Fri, 25 Feb 2022 08:27:12 +0100 Subject: [PATCH 2/7] Extending thoughts --- src/timer.rs | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/src/timer.rs b/src/timer.rs index 5e24044cb..011cdb8a0 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -11,6 +11,8 @@ //! [examples/adc.rs]: https://github.com/stm32-rs/stm32f3xx-hal/blob/v0.9.0/examples/adc.rs use core::convert::{From, TryFrom}; +use core::marker::PhantomData; +use core::ops::Deref; use crate::pac::{DCB, DWT}; #[cfg(feature = "enumset")] @@ -592,3 +594,45 @@ cfg_if::cfg_if! { fn test(tim: pac::TIM16) { let tim6: *const pac::tim6::RegisterBlock = unsafe {core::mem::transmute(pac::TIM16::ptr())}; } + +struct BasicTimer { + _ptr: usize, + real_timer: PhantomData, +} + +impl Deref for BasicTimer { + type Target = pac::tim6::RegisterBlock; + + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*(self._ptr as *const Self::Target) } + } +} + +impl From for BasicTimer { + fn from(tim: pac::TIM6) -> Self { + Self { + _ptr: unsafe { pac::TIM6::ptr() as _ }, + real_timer: PhantomData, + } + } +} + +impl BasicTimer { + pub fn free(self) -> T { + self.real_timer + } +} + +// TODO: Is that trait needed, when we already have Into? +pub trait BasicTimerInstance: Deref {} +impl BasicTimerInstance for BasicTimer {} + +fn test2(tim: impl Into>) { + let tim: BasicTimer = tim.into(); + tim.cr1.read(); +} + +fn test3(tim: pac::TIM6) { + test2(tim); +} From 956c469c374f7069d267f305080def31888e9170 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fabian=20Vi=C3=B6l?= Date: Fri, 25 Feb 2022 08:28:24 +0100 Subject: [PATCH 3/7] No need for phanton data --- src/timer.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/timer.rs b/src/timer.rs index 011cdb8a0..e928bba42 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -597,7 +597,7 @@ fn test(tim: pac::TIM16) { struct BasicTimer { _ptr: usize, - real_timer: PhantomData, + real_timer: T, } impl Deref for BasicTimer { @@ -613,7 +613,7 @@ impl From for BasicTimer { fn from(tim: pac::TIM6) -> Self { Self { _ptr: unsafe { pac::TIM6::ptr() as _ }, - real_timer: PhantomData, + real_timer: tim, } } } From fce730dcd8126d27e3e47dd69d85f30e4450585f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fabian=20Vi=C3=B6l?= Date: Fri, 25 Feb 2022 17:56:43 +0100 Subject: [PATCH 4/7] Notes --- src/timer.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/timer.rs b/src/timer.rs index e928bba42..44e06a337 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -595,6 +595,8 @@ fn test(tim: pac::TIM16) { let tim6: *const pac::tim6::RegisterBlock = unsafe {core::mem::transmute(pac::TIM16::ptr())}; } +// TODO: Rename BasicTimer to BasicTimerPeripheral or similar to not be confusing +// by the actual Timer??? or in general, this could replace the Timer implementation? struct BasicTimer { _ptr: usize, real_timer: T, From 5ff1d0517220ff154566f6ace8cd9a4ce2c1515a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fabian=20Vi=C3=B6l?= Date: Sun, 6 Mar 2022 23:06:31 +0100 Subject: [PATCH 5/7] WIP: Drafting deref based impl Testsuite is NOT working :( --- src/timer.rs | 97 +++++++++++++++++++++++++++++++--------------------- 1 file changed, 58 insertions(+), 39 deletions(-) diff --git a/src/timer.rs b/src/timer.rs index 44e06a337..971f7dd82 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -90,7 +90,7 @@ impl Instant { #[derive(Debug)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub struct Timer { - tim: TIM, + tim: BasicTimer, clocks: Clocks, } @@ -110,7 +110,7 @@ pub enum Event { impl Timer where - TIM: Instance, + TIM: Instance, { /// Configures a TIM peripheral as a periodic count down timer // TODO: CHange clocks to be a global variable @@ -118,13 +118,15 @@ where TIM::enable(apb); TIM::reset(apb); + let tim: BasicTimer<_> = tim.into(); + Timer { clocks, tim } } /// Stops the timer #[inline] pub fn stop(&mut self) { - self.tim.set_cr1_cen(false); + self.tim.cr1.modify(|_, w| w.cen().disabled()); } /// Enable or disable the interrupt for the specified [`Event`]. @@ -166,7 +168,7 @@ where #[inline] pub fn configure_interrupt(&mut self, event: Event, enable: bool) { match event { - Event::Update => self.tim.set_dier_uie(enable), + Event::Update => self.tim.dier.modify(|_, w| w.uie().bit(enable)), } } @@ -190,7 +192,7 @@ where #[inline] pub fn is_interrupt_configured(&self, event: Event) -> bool { match event { - Event::Update => self.tim.is_dier_uie_set(), + Event::Update => self.tim.dier.read().uie().bit(), } } @@ -214,7 +216,7 @@ where /// Check if an interrupt event happened. pub fn is_event_triggered(&self, event: Event) -> bool { match event { - Event::Update => self.tim.is_sr_uief_set(), + Event::Update => self.tim.sr.read().uif().is_update_pending(), } } @@ -237,14 +239,15 @@ where #[inline] pub fn clear_event(&mut self, event: Event) { match event { - Event::Update => self.tim.clear_sr_uief(), + Event::Update => self.tim.sr.modify(|_, w| w.uif().clear()), } } /// Clear **all** interrupt events. #[inline] pub fn clear_events(&mut self) { - self.tim.clear_sr(); + // SAFETY: This atomic write clears all flags and ignores the reserverd bit fields. + self.tim.sr.write(|w| unsafe { w.bits(0) }); } /// Get access to the underlying register block. @@ -257,22 +260,22 @@ where /// Changing specific options can lead to un-expected behavior and nothing /// is guaranteed. pub unsafe fn peripheral(&mut self) -> &mut TIM { - &mut self.tim + &mut self.tim.real_timer } /// Releases the TIM peripheral #[inline] pub fn free(mut self) -> TIM { self.stop(); - self.tim + self.tim.real_timer } } -impl Periodic for Timer where TIM: Instance {} +impl Periodic for Timer where TIM: Instance {} impl CountDown for Timer where - TIM: Instance, + TIM: Instance, { type Time = duration::Generic; @@ -288,10 +291,13 @@ where let ticks = clock.integer() * *timeout.scaling_factor() * timeout.integer(); let psc = crate::unwrap!(u16::try_from((ticks - 1) / (1 << 16)).ok()); - self.tim.set_psc(psc); + // NOTE(write): uses all bits in this register. + self.tim.psc.write(|w| w.psc().bits(psc)); let arr = crate::unwrap!(u16::try_from(ticks / u32::from(psc + 1)).ok()); - self.tim.set_arr(arr); + // TODO(Sh3Rm4n): + // self.tim.arr.write(|w| { w.arr().bits(arr) }); + self.tim.arr.write(|w| unsafe { w.bits(u32::from(arr)) }); // Ensure that the below procedure does not create an unexpected interrupt. let is_update_interrupt_active = self.is_interrupt_configured(Event::Update); @@ -301,7 +307,7 @@ where // Trigger an update event to load the prescaler value to the clock The above line raises // an update event which will indicate that the timer is already finished. - self.tim.set_egr_ug(); + self.tim.egr.write(|w| w.ug().update()); // Since this is not the case, it should be cleared. self.clear_event(Event::Update); @@ -310,13 +316,13 @@ where } // start counter - self.tim.set_cr1_cen(true); + self.tim.cr1.modify(|_, w| w.cen().bit(true)); } /// Wait until [`Event::Update`] / the timer has elapsed /// and than clear the event. fn wait(&mut self) -> nb::Result<(), Void> { - if !self.tim.is_sr_uief_set() { + if !self.tim.sr.read().uif().is_update_pending() { Err(nb::Error::WouldBlock) } else { self.clear_event(Event::Update); @@ -332,12 +338,12 @@ pub struct AlreadyCancled; impl Cancel for Timer where - TIM: Instance, + TIM: Instance, { type Error = AlreadyCancled; fn cancel(&mut self) -> Result<(), Self::Error> { // If timer is already stopped. - if !self.tim.is_cr1_cen_set() { + if !self.tim.cr1.read().cen().bit() { return Err(AlreadyCancled); } self.stop(); @@ -376,8 +382,8 @@ pub trait CommonRegisterBlock: crate::private::Sealed { } /// Associated clocks with timers -pub trait Instance: - CommonRegisterBlock +pub trait Instance: + Into> + crate::interrupts::InterruptNumber + crate::private::Sealed + rcc::Enable @@ -389,6 +395,17 @@ pub trait Instance: macro_rules! timer { ($TIMX:ident) => { + // TODO: This must be associated, so that Into trait works? + impl From for BasicTimer { + fn from(tim: crate::pac::$TIMX) -> Self { + Self { + // TODO: Check if TIM6 is really common ground for all timer. + _ptr: unsafe { pac::TIM6::ptr() as _ }, + real_timer: tim, + } + } + } + impl CommonRegisterBlock for crate::pac::$TIMX { #[inline] fn set_cr1_cen(&mut self, enable: bool) { @@ -452,7 +469,7 @@ macro_rules! timer { macro_rules! timer_var_clock { ($($TIMX:ident, $timXsw:ident),+) => { $( - impl Instance for crate::pac::$TIMX { + impl Instance for crate::pac::$TIMX { #[inline] fn clock(clocks: &Clocks) -> Hertz { // SAFETY: Atomic read with no side-effects. @@ -496,7 +513,7 @@ macro_rules! timer_var_clock { macro_rules! timer_static_clock { ($($TIMX:ident),+) => { $( - impl Instance for crate::pac::$TIMX { + impl Instance for crate::pac::$TIMX { #[inline] fn clock(clocks: &Clocks) -> Hertz { ::timer_clock(clocks) @@ -597,7 +614,9 @@ fn test(tim: pac::TIM16) { // TODO: Rename BasicTimer to BasicTimerPeripheral or similar to not be confusing // by the actual Timer??? or in general, this could replace the Timer implementation? -struct BasicTimer { +#[derive(Debug)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub struct BasicTimer { _ptr: usize, real_timer: T, } @@ -610,21 +629,21 @@ impl Deref for BasicTimer { unsafe { &*(self._ptr as *const Self::Target) } } } - -impl From for BasicTimer { - fn from(tim: pac::TIM6) -> Self { - Self { - _ptr: unsafe { pac::TIM6::ptr() as _ }, - real_timer: tim, - } - } -} - -impl BasicTimer { - pub fn free(self) -> T { - self.real_timer - } -} +// +// impl From for BasicTimer { +// fn from(tim: pac::TIM6) -> Self { +// Self { +// _ptr: unsafe { pac::TIM6::ptr() as _ }, +// real_timer: tim, +// } +// } +// } + +// impl BasicTimer { +// pub fn free(self) -> T { +// self.real_timer +// } +// } // TODO: Is that trait needed, when we already have Into? pub trait BasicTimerInstance: Deref {} From 8fac9f0344f9121542f447de32a87cafbba6de21 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fabian=20Vi=C3=B6l?= Date: Mon, 7 Mar 2022 22:01:49 +0100 Subject: [PATCH 6/7] Use AsBasicTimer trait timer test is running again! --- src/timer.rs | 66 ++++++++++++++++++++++++++++++++-------------------- 1 file changed, 41 insertions(+), 25 deletions(-) diff --git a/src/timer.rs b/src/timer.rs index 971f7dd82..7f5e65af7 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -90,7 +90,7 @@ impl Instant { #[derive(Debug)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] pub struct Timer { - tim: BasicTimer, + tim: TIM, clocks: Clocks, } @@ -110,7 +110,7 @@ pub enum Event { impl Timer where - TIM: Instance, + TIM: Instance, { /// Configures a TIM peripheral as a periodic count down timer // TODO: CHange clocks to be a global variable @@ -118,15 +118,13 @@ where TIM::enable(apb); TIM::reset(apb); - let tim: BasicTimer<_> = tim.into(); - Timer { clocks, tim } } /// Stops the timer #[inline] pub fn stop(&mut self) { - self.tim.cr1.modify(|_, w| w.cen().disabled()); + self.tim.as_basic_timer_mut().cr1.modify(|_, w| w.cen().disabled()); } /// Enable or disable the interrupt for the specified [`Event`]. @@ -168,7 +166,7 @@ where #[inline] pub fn configure_interrupt(&mut self, event: Event, enable: bool) { match event { - Event::Update => self.tim.dier.modify(|_, w| w.uie().bit(enable)), + Event::Update => self.tim.as_basic_timer_mut().dier.modify(|_, w| w.uie().bit(enable)), } } @@ -192,7 +190,7 @@ where #[inline] pub fn is_interrupt_configured(&self, event: Event) -> bool { match event { - Event::Update => self.tim.dier.read().uie().bit(), + Event::Update => self.tim.as_basic_timer().dier.read().uie().bit(), } } @@ -216,7 +214,7 @@ where /// Check if an interrupt event happened. pub fn is_event_triggered(&self, event: Event) -> bool { match event { - Event::Update => self.tim.sr.read().uif().is_update_pending(), + Event::Update => self.tim.as_basic_timer().sr.read().uif().is_update_pending(), } } @@ -239,7 +237,7 @@ where #[inline] pub fn clear_event(&mut self, event: Event) { match event { - Event::Update => self.tim.sr.modify(|_, w| w.uif().clear()), + Event::Update => self.tim.as_basic_timer_mut().sr.modify(|_, w| w.uif().clear()), } } @@ -247,7 +245,7 @@ where #[inline] pub fn clear_events(&mut self) { // SAFETY: This atomic write clears all flags and ignores the reserverd bit fields. - self.tim.sr.write(|w| unsafe { w.bits(0) }); + self.tim.as_basic_timer_mut().sr.write(|w| unsafe { w.bits(0) }); } /// Get access to the underlying register block. @@ -260,22 +258,22 @@ where /// Changing specific options can lead to un-expected behavior and nothing /// is guaranteed. pub unsafe fn peripheral(&mut self) -> &mut TIM { - &mut self.tim.real_timer + &mut self.tim } /// Releases the TIM peripheral #[inline] pub fn free(mut self) -> TIM { self.stop(); - self.tim.real_timer + self.tim } } -impl Periodic for Timer where TIM: Instance {} +impl Periodic for Timer where TIM: Instance {} impl CountDown for Timer where - TIM: Instance, + TIM: Instance, { type Time = duration::Generic; @@ -292,12 +290,12 @@ where let psc = crate::unwrap!(u16::try_from((ticks - 1) / (1 << 16)).ok()); // NOTE(write): uses all bits in this register. - self.tim.psc.write(|w| w.psc().bits(psc)); + self.tim.as_basic_timer_mut().psc.write(|w| w.psc().bits(psc)); let arr = crate::unwrap!(u16::try_from(ticks / u32::from(psc + 1)).ok()); // TODO(Sh3Rm4n): // self.tim.arr.write(|w| { w.arr().bits(arr) }); - self.tim.arr.write(|w| unsafe { w.bits(u32::from(arr)) }); + self.tim.as_basic_timer_mut().arr.write(|w| unsafe { w.bits(u32::from(arr)) }); // Ensure that the below procedure does not create an unexpected interrupt. let is_update_interrupt_active = self.is_interrupt_configured(Event::Update); @@ -307,7 +305,7 @@ where // Trigger an update event to load the prescaler value to the clock The above line raises // an update event which will indicate that the timer is already finished. - self.tim.egr.write(|w| w.ug().update()); + self.tim.as_basic_timer_mut().egr.write(|w| w.ug().update()); // Since this is not the case, it should be cleared. self.clear_event(Event::Update); @@ -316,13 +314,13 @@ where } // start counter - self.tim.cr1.modify(|_, w| w.cen().bit(true)); + self.tim.as_basic_timer_mut().cr1.modify(|_, w| w.cen().bit(true)); } /// Wait until [`Event::Update`] / the timer has elapsed /// and than clear the event. fn wait(&mut self) -> nb::Result<(), Void> { - if !self.tim.sr.read().uif().is_update_pending() { + if !self.tim.as_basic_timer().sr.read().uif().is_update_pending() { Err(nb::Error::WouldBlock) } else { self.clear_event(Event::Update); @@ -338,12 +336,12 @@ pub struct AlreadyCancled; impl Cancel for Timer where - TIM: Instance, + TIM: Instance, { type Error = AlreadyCancled; fn cancel(&mut self) -> Result<(), Self::Error> { // If timer is already stopped. - if !self.tim.cr1.read().cen().bit() { + if !self.tim.as_basic_timer().cr1.read().cen().bit() { return Err(AlreadyCancled); } self.stop(); @@ -382,8 +380,8 @@ pub trait CommonRegisterBlock: crate::private::Sealed { } /// Associated clocks with timers -pub trait Instance: - Into> +pub trait Instance: + AsBasicTimer + crate::interrupts::InterruptNumber + crate::private::Sealed + rcc::Enable @@ -406,6 +404,17 @@ macro_rules! timer { } } + impl AsBasicTimer for crate::pac::$TIMX { + fn as_basic_timer(&self) -> &pac::tim6::RegisterBlock { + unsafe {&*(crate::pac::$TIMX::ptr() as *const pac::tim6::RegisterBlock)} + // unsafe { &*(self._ptr as *const Self::Target) } + } + + fn as_basic_timer_mut(&mut self) -> &mut pac::tim6::RegisterBlock { + unsafe {&mut *(crate::pac::$TIMX::ptr() as *mut pac::tim6::RegisterBlock)} + } + } + impl CommonRegisterBlock for crate::pac::$TIMX { #[inline] fn set_cr1_cen(&mut self, enable: bool) { @@ -469,7 +478,7 @@ macro_rules! timer { macro_rules! timer_var_clock { ($($TIMX:ident, $timXsw:ident),+) => { $( - impl Instance for crate::pac::$TIMX { + impl Instance for crate::pac::$TIMX { #[inline] fn clock(clocks: &Clocks) -> Hertz { // SAFETY: Atomic read with no side-effects. @@ -513,7 +522,7 @@ macro_rules! timer_var_clock { macro_rules! timer_static_clock { ($($TIMX:ident),+) => { $( - impl Instance for crate::pac::$TIMX { + impl Instance for crate::pac::$TIMX { #[inline] fn clock(clocks: &Clocks) -> Hertz { ::timer_clock(clocks) @@ -649,6 +658,13 @@ impl Deref for BasicTimer { pub trait BasicTimerInstance: Deref {} impl BasicTimerInstance for BasicTimer {} +// TODO: +pub trait AsBasicTimer { + fn as_basic_timer(&self) -> &pac::tim6::RegisterBlock; + + fn as_basic_timer_mut(&mut self) -> &mut pac::tim6::RegisterBlock; +} + fn test2(tim: impl Into>) { let tim: BasicTimer = tim.into(); tim.cr1.read(); From f7c8ebdba63a8b67973c92fad16da68abe3619c8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fabian=20Vi=C3=B6l?= Date: Mon, 7 Mar 2022 22:02:23 +0100 Subject: [PATCH 7/7] Format --- src/timer.rs | 60 +++++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 48 insertions(+), 12 deletions(-) diff --git a/src/timer.rs b/src/timer.rs index 7f5e65af7..9b9b98ba8 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -124,7 +124,10 @@ where /// Stops the timer #[inline] pub fn stop(&mut self) { - self.tim.as_basic_timer_mut().cr1.modify(|_, w| w.cen().disabled()); + self.tim + .as_basic_timer_mut() + .cr1 + .modify(|_, w| w.cen().disabled()); } /// Enable or disable the interrupt for the specified [`Event`]. @@ -166,7 +169,11 @@ where #[inline] pub fn configure_interrupt(&mut self, event: Event, enable: bool) { match event { - Event::Update => self.tim.as_basic_timer_mut().dier.modify(|_, w| w.uie().bit(enable)), + Event::Update => self + .tim + .as_basic_timer_mut() + .dier + .modify(|_, w| w.uie().bit(enable)), } } @@ -214,7 +221,13 @@ where /// Check if an interrupt event happened. pub fn is_event_triggered(&self, event: Event) -> bool { match event { - Event::Update => self.tim.as_basic_timer().sr.read().uif().is_update_pending(), + Event::Update => self + .tim + .as_basic_timer() + .sr + .read() + .uif() + .is_update_pending(), } } @@ -237,7 +250,11 @@ where #[inline] pub fn clear_event(&mut self, event: Event) { match event { - Event::Update => self.tim.as_basic_timer_mut().sr.modify(|_, w| w.uif().clear()), + Event::Update => self + .tim + .as_basic_timer_mut() + .sr + .modify(|_, w| w.uif().clear()), } } @@ -245,7 +262,10 @@ where #[inline] pub fn clear_events(&mut self) { // SAFETY: This atomic write clears all flags and ignores the reserverd bit fields. - self.tim.as_basic_timer_mut().sr.write(|w| unsafe { w.bits(0) }); + self.tim + .as_basic_timer_mut() + .sr + .write(|w| unsafe { w.bits(0) }); } /// Get access to the underlying register block. @@ -290,12 +310,18 @@ where let psc = crate::unwrap!(u16::try_from((ticks - 1) / (1 << 16)).ok()); // NOTE(write): uses all bits in this register. - self.tim.as_basic_timer_mut().psc.write(|w| w.psc().bits(psc)); + self.tim + .as_basic_timer_mut() + .psc + .write(|w| w.psc().bits(psc)); let arr = crate::unwrap!(u16::try_from(ticks / u32::from(psc + 1)).ok()); // TODO(Sh3Rm4n): // self.tim.arr.write(|w| { w.arr().bits(arr) }); - self.tim.as_basic_timer_mut().arr.write(|w| unsafe { w.bits(u32::from(arr)) }); + self.tim + .as_basic_timer_mut() + .arr + .write(|w| unsafe { w.bits(u32::from(arr)) }); // Ensure that the below procedure does not create an unexpected interrupt. let is_update_interrupt_active = self.is_interrupt_configured(Event::Update); @@ -314,13 +340,23 @@ where } // start counter - self.tim.as_basic_timer_mut().cr1.modify(|_, w| w.cen().bit(true)); + self.tim + .as_basic_timer_mut() + .cr1 + .modify(|_, w| w.cen().bit(true)); } /// Wait until [`Event::Update`] / the timer has elapsed /// and than clear the event. fn wait(&mut self) -> nb::Result<(), Void> { - if !self.tim.as_basic_timer().sr.read().uif().is_update_pending() { + if !self + .tim + .as_basic_timer() + .sr + .read() + .uif() + .is_update_pending() + { Err(nb::Error::WouldBlock) } else { self.clear_event(Event::Update); @@ -406,12 +442,12 @@ macro_rules! timer { impl AsBasicTimer for crate::pac::$TIMX { fn as_basic_timer(&self) -> &pac::tim6::RegisterBlock { - unsafe {&*(crate::pac::$TIMX::ptr() as *const pac::tim6::RegisterBlock)} + unsafe { &*(crate::pac::$TIMX::ptr() as *const pac::tim6::RegisterBlock) } // unsafe { &*(self._ptr as *const Self::Target) } } fn as_basic_timer_mut(&mut self) -> &mut pac::tim6::RegisterBlock { - unsafe {&mut *(crate::pac::$TIMX::ptr() as *mut pac::tim6::RegisterBlock)} + unsafe { &mut *(crate::pac::$TIMX::ptr() as *mut pac::tim6::RegisterBlock) } } } @@ -618,7 +654,7 @@ cfg_if::cfg_if! { } fn test(tim: pac::TIM16) { - let tim6: *const pac::tim6::RegisterBlock = unsafe {core::mem::transmute(pac::TIM16::ptr())}; + let tim6: *const pac::tim6::RegisterBlock = unsafe { core::mem::transmute(pac::TIM16::ptr()) }; } // TODO: Rename BasicTimer to BasicTimerPeripheral or similar to not be confusing