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Take concrete Hertz type
- Remove generic TryFrom constraint on functions taking a Rate type - Make all functions taking a Rate type take the Hertz type instead
1 parent 9b082a2 commit c6bd1ce

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7 files changed

+47
-91
lines changed

7 files changed

+47
-91
lines changed

‎examples/can.rs

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -32,14 +32,10 @@ fn main() -> ! {
3232

3333
let _clocks = rcc
3434
.cfgr
35-
.use_hse(32u32.MHz())
36-
.unwrap()
37-
.sysclk(32u32.MHz())
38-
.unwrap()
39-
.pclk1(16u32.MHz())
40-
.unwrap()
41-
.pclk2(16u32.MHz())
42-
.unwrap()
35+
.use_hse(Hertz(32_000_000))
36+
.sysclk(Hertz(32_000_000))
37+
.pclk1(Hertz(16_000_000))
38+
.pclk2(Hertz(16_000_000))
4339
.freeze(&mut flash.acr);
4440

4541
// Configure CAN RX and TX pins (AF9)

‎examples/pwm.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ fn main() -> ! {
2828
// Configure our clocks
2929
let mut flash = dp.FLASH.constrain();
3030
let mut rcc = dp.RCC.constrain();
31-
let clocks = rcc.cfgr.sysclk(16u32.MHz()).unwrap().freeze(&mut flash.acr);
31+
let clocks = rcc.cfgr.sysclk(Hertz(16_000_000)).freeze(&mut flash.acr);
3232

3333
// Prep the pins we need in their correct alternate function
3434
let mut gpioa = dp.GPIOA.split(&mut rcc.ahb);

‎examples/spi.rs

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -25,12 +25,9 @@ fn main() -> ! {
2525

2626
let clocks = rcc
2727
.cfgr
28-
.use_hse(8u32.MHz())
29-
.unwrap()
30-
.sysclk(48u32.MHz())
31-
.unwrap()
32-
.pclk1(24u32.MHz())
33-
.unwrap()
28+
.use_hse(Hertz(8_000_000))
29+
.sysclk(Hertz(48_000_000))
30+
.pclk1(Hertz(24_000_000))
3431
.freeze(&mut flash.acr);
3532

3633
// Configure pins for SPI

‎examples/usb_serial.rs

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -27,14 +27,10 @@ fn main() -> ! {
2727

2828
let clocks = rcc
2929
.cfgr
30-
.use_hse(8u32.MHz())
31-
.unwrap()
32-
.sysclk(48u32.MHz())
33-
.unwrap()
34-
.pclk1(24u32.MHz())
35-
.unwrap()
36-
.pclk2(24u32.MHz())
37-
.unwrap()
30+
.use_hse(Hertz(8_000_000))
31+
.sysclk(Hertz(48_000_000))
32+
.pclk1(Hertz(24_000_000))
33+
.pclk2(Hertz(24_000_000))
3834
.freeze(&mut flash.acr);
3935

4036
assert!(clocks.usbclk_valid());

‎src/rcc.rs

Lines changed: 16 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -54,15 +54,13 @@
5454
//! For more details read the documentation of the [`CFGR`] methods to
5555
//! find out how to setup the clock.
5656
57-
use core::convert::TryInto;
58-
5957
use crate::pac::{
6058
rcc::{self, cfgr, cfgr2},
6159
RCC,
6260
};
6361

6462
use crate::flash::ACR;
65-
use crate::time::rate::{Hertz, Rate};
63+
use crate::time::rate::Hertz;
6664

6765
/// Extension trait that constrains the `RCC` peripheral
6866
pub trait RccExt {
@@ -335,12 +333,9 @@ impl CFGR {
335333
///
336334
/// Will result in a hang if an external oscillator is not connected or it fails to start,
337335
/// unless [css](CFGR::enable_css) is enabled.
338-
pub fn use_hse<F>(mut self, freq: F) -> Result<Self, <F as TryInto<Hertz<u32>>>::Error>
339-
where
340-
F: Rate + TryInto<Hertz<u32>>,
341-
{
342-
self.hse = Some((freq.try_into()? as Hertz).0);
343-
Ok(self)
336+
pub fn use_hse(mut self, freq: Hertz) -> Self {
337+
self.hse = Some(freq.0);
338+
self
344339
}
345340

346341
/// Enable `HSE` bypass.
@@ -366,12 +361,9 @@ impl CFGR {
366361
}
367362

368363
/// Sets a frequency for the AHB bus
369-
pub fn hclk<F>(mut self, freq: F) -> Result<Self, <F as TryInto<Hertz<u32>>>::Error>
370-
where
371-
F: Rate + TryInto<Hertz<u32>>,
372-
{
373-
self.hclk = Some((freq.try_into()? as Hertz).0);
374-
Ok(self)
364+
pub fn hclk(mut self, freq: Hertz) -> Self {
365+
self.hclk = Some(freq.0);
366+
self
375367
}
376368

377369
/// Sets a frequency for the `APB1` bus
@@ -380,12 +372,9 @@ impl CFGR {
380372
///
381373
/// If not manually set, it will be set to [`CFGR::sysclk`] frequency
382374
/// or [`CFGR::sysclk`] frequency / 2, if [`CFGR::sysclk`] > 36 Mhz
383-
pub fn pclk1<F>(mut self, freq: F) -> Result<Self, <F as TryInto<Hertz<u32>>>::Error>
384-
where
385-
F: Rate + TryInto<Hertz<u32>>,
386-
{
387-
self.pclk1 = Some((freq.try_into()? as Hertz).0);
388-
Ok(self)
375+
pub fn pclk1(mut self, freq: Hertz) -> Self {
376+
self.pclk1 = Some(freq.0);
377+
self
389378
}
390379

391380
/// Sets a frequency for the `APB2` bus
@@ -401,12 +390,9 @@ impl CFGR {
401390
///
402391
/// [stm32f302xd,stm32f302xe,stm32f303xd,stm32f303xe,stm32f398]
403392
///
404-
pub fn pclk2<F>(mut self, freq: F) -> Result<Self, <F as TryInto<Hertz<u32>>>::Error>
405-
where
406-
F: Rate + TryInto<Hertz<u32>>,
407-
{
408-
self.pclk2 = Some((freq.try_into()? as Hertz).0);
409-
Ok(self)
393+
pub fn pclk2(mut self, freq: Hertz) -> Self {
394+
self.pclk2 = Some(freq.0);
395+
self
410396
}
411397

412398
/// Sets the system (core) frequency
@@ -424,12 +410,9 @@ impl CFGR {
424410
/// even when using the internal oscillator:
425411
///
426412
/// [stm32f302xd,stm32f302xe,stm32f303xd,stm32f303xe,stm32f398]
427-
pub fn sysclk<F>(mut self, freq: F) -> Result<Self, <F as TryInto<Hertz<u32>>>::Error>
428-
where
429-
F: Rate + TryInto<Hertz<u32>>,
430-
{
431-
self.sysclk = Some((freq.try_into()? as Hertz).0);
432-
Ok(self)
413+
pub fn sysclk(mut self, freq: Hertz) -> Self {
414+
self.sysclk = Some(freq.0);
415+
self
433416
}
434417

435418
/// Calculate the values for the pll multiplier (`PLLMUL`) and the pll divisior (`PLLDIV`).

‎src/timer.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -91,7 +91,7 @@ macro_rules! hal {
9191

9292
fn start<T>(&mut self, timeout: T)
9393
where
94-
T: Into<Hertz>,
94+
T: Into<Self::Time>,
9595
{
9696
self.stop();
9797

‎tests/rcc.rs

Lines changed: 18 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -37,10 +37,8 @@ mod tests {
3737

3838
let clock = rcc
3939
.cfgr
40-
.use_hse(8u32.MHz())
41-
.unwrap()
42-
.sysclk(15u32.MHz())
43-
.unwrap()
40+
.use_hse(Hertz(8_000_000))
41+
.sysclk(Hertz(15_000_000))
4442
.freeze(&mut flash.acr);
4543

4644
defmt::assert!(clock.sysclk() == 15u32.MHz());
@@ -66,7 +64,7 @@ mod tests {
6664
feature = "stm32f303xe",
6765
feature = "stm32f398",
6866
))] {
69-
let clock = rcc.cfgr.sysclk(72u32.MHz()).unwrap().freeze(&mut flash.acr);
67+
let clock = rcc.cfgr.sysclk(Hertz(72_000_000)).freeze(&mut flash.acr);
7068

7169
defmt::assert!(clock.sysclk() == 72u32.MHz());
7270
defmt::assert!(clock.hclk() == 72u32.MHz());
@@ -80,7 +78,7 @@ mod tests {
8078
// and the resolution is therefor lower.
8179
// Because of the implementation the clock is then approximated to
8280
// the highest possible value (64 Mhz).
83-
let clock = rcc.cfgr.sysclk(67u32.MHz()).unwrap().freeze(&mut flash.acr);
81+
let clock = rcc.cfgr.sysclk(Hertz(67_000_000)).freeze(&mut flash.acr);
8482

8583
defmt::assert!(clock.sysclk() == 64u32.MHz());
8684
defmt::assert!(clock.hclk() == 64u32.MHz());
@@ -102,10 +100,8 @@ mod tests {
102100

103101
let clock = rcc
104102
.cfgr
105-
.use_hse(8u32.MHz())
106-
.unwrap()
107-
.sysclk(32u32.MHz())
108-
.unwrap()
103+
.use_hse(Hertz(8_000_000))
104+
.sysclk(Hertz(32_000_000))
109105
.freeze(&mut flash.acr);
110106

111107
defmt::assert!(clock.sysclk() == 32u32.MHz());
@@ -126,10 +122,8 @@ mod tests {
126122

127123
let clock = rcc
128124
.cfgr
129-
.use_hse(8u32.MHz())
130-
.unwrap()
131-
.sysclk(48u32.MHz())
132-
.unwrap()
125+
.use_hse(Hertz(8_000_000))
126+
.sysclk(Hertz(48_000_000))
133127
.freeze(&mut flash.acr); // works
134128

135129
defmt::assert!(clock.sysclk() == 48u32.MHz());
@@ -148,16 +142,11 @@ mod tests {
148142

149143
let clock = rcc
150144
.cfgr
151-
.use_hse(8u32.MHz())
152-
.unwrap()
153-
.hclk(48u32.MHz())
154-
.unwrap()
155-
.sysclk(48u32.MHz())
156-
.unwrap()
157-
.pclk1(12u32.MHz())
158-
.unwrap()
159-
.pclk2(12u32.MHz())
160-
.unwrap()
145+
.use_hse(Hertz(8_000_000))
146+
.hclk(Hertz(48_000_000))
147+
.sysclk(Hertz(48_000_000))
148+
.pclk1(Hertz(12_000_000))
149+
.pclk2(Hertz(12_000_000))
161150
.freeze(&mut flash.acr);
162151

163152
defmt::assert!(clock.sysclk() == 48u32.MHz());
@@ -177,12 +166,9 @@ mod tests {
177166

178167
let clock = rcc
179168
.cfgr
180-
.use_hse(8u32.MHz())
181-
.unwrap()
182-
.pclk1(16u32.MHz())
183-
.unwrap()
184-
.sysclk(64u32.MHz())
185-
.unwrap()
169+
.use_hse(Hertz(8_000_000))
170+
.pclk1(Hertz(16_000_000))
171+
.sysclk(Hertz(64_000_000))
186172
.freeze(&mut flash.acr);
187173

188174
defmt::assert!(clock.sysclk() == 64u32.MHz());
@@ -203,10 +189,8 @@ mod tests {
203189

204190
let clock = rcc
205191
.cfgr
206-
.use_hse(8u32.MHz())
207-
.unwrap()
208-
.sysclk(72u32.MHz())
209-
.unwrap()
192+
.use_hse(Hertz(8_000_000))
193+
.sysclk(Hertz(72_000_000))
210194
.freeze(&mut flash.acr);
211195

212196
defmt::assert!(clock.sysclk() == 72u32.MHz());

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