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refactor CkMode and Align
1 parent 153b51a commit 776c5fd

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2 files changed

+22
-26
lines changed

2 files changed

+22
-26
lines changed

examples/adc.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ fn main() -> ! {
2525
// correctly.
2626
&mut dp.ADC1_2,
2727
&mut rcc.ahb,
28-
adc::CKMODE::default(),
28+
adc::CkMode::default(),
2929
clocks,
3030
);
3131

src/adc.rs

Lines changed: 21 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ use crate::{
1515
gpio::{gpioa, gpiob, gpioc},
1616
pac::{ADC1, ADC1_2, ADC2},
1717
};
18-
use stm32f3::stm32f303::adc1_2::ccr::CKMODE_A;
18+
use stm32f3::stm32f303::{adc1::cfgr::ALIGN_A, adc1_2::ccr::CKMODE_A};
1919
const MAX_ADVREGEN_STARTUP_US: u32 = 10;
2020

2121
#[cfg(any(
@@ -35,7 +35,7 @@ use crate::{
3535
pub struct Adc<ADC> {
3636
pub rb: ADC,
3737
clocks: Clocks,
38-
ckmode: CKMODE,
38+
ckmode: CkMode,
3939
operation_mode: Option<OperationMode>,
4040
}
4141

@@ -88,30 +88,29 @@ pub enum OperationMode {
8888
}
8989

9090
#[derive(Clone, Copy, PartialEq)]
91-
/// ADC CKMODE
91+
/// ADC CkMode
9292
// TODO: Add ASYNCHRONOUS mode
93-
pub enum CKMODE {
93+
pub enum CkMode {
9494
// ASYNCHRONOUS = 0,
9595
SYNCDIV1 = 1,
9696
SYNCDIV2 = 2,
9797
SYNCDIV4 = 4,
9898
}
9999

100-
impl Default for CKMODE {
100+
impl Default for CkMode {
101101
fn default() -> Self {
102-
CKMODE::SYNCDIV2
102+
CkMode::SYNCDIV2
103103
}
104104
}
105105

106106
// ADC3_2 returns a pointer to a adc1_2 type, so this from is ok for both.
107-
#[cfg(feature = "stm32f303")]
108-
impl From<CKMODE> for CKMODE_A {
109-
fn from(ckmode: CKMODE) -> Self {
107+
impl From<CkMode> for CKMODE_A {
108+
fn from(ckmode: CkMode) -> Self {
110109
match ckmode {
111-
//CKMODE::ASYNCHRONOUS => CKMODE_A::ASYNCHRONOUS,
112-
CKMODE::SYNCDIV1 => CKMODE_A::SYNCDIV1,
113-
CKMODE::SYNCDIV2 => CKMODE_A::SYNCDIV2,
114-
CKMODE::SYNCDIV4 => CKMODE_A::SYNCDIV4,
110+
//CkMode::ASYNCHRONOUS => CKMODE_A::ASYNCHRONOUS,
111+
CkMode::SYNCDIV1 => CKMODE_A::SYNCDIV1,
112+
CkMode::SYNCDIV2 => CKMODE_A::SYNCDIV2,
113+
CkMode::SYNCDIV4 => CKMODE_A::SYNCDIV4,
115114
}
116115
}
117116
}
@@ -130,12 +129,11 @@ impl Default for Align {
130129
}
131130
}
132131

133-
impl Align {
134-
/// Conversion to bits for ALIGN in ADCx_CFGR
135-
fn bitvalue(&self) -> bool {
136-
match self {
137-
Align::Right => false,
138-
Align::Left => true,
132+
impl From<Align> for ALIGN_A {
133+
fn from(align: Align) -> ALIGN_A {
134+
match align {
135+
Align::Right => ALIGN_A::RIGHT,
136+
Align::Left => ALIGN_A::LEFT,
139137
}
140138
}
141139
}
@@ -297,7 +295,7 @@ macro_rules! adc_hal {
297295
rb: $ADC,
298296
adc_common : &mut $ADC_COMMON,
299297
ahb: &mut AHB,
300-
ckmode: CKMODE,
298+
ckmode: CkMode,
301299
clocks: Clocks,
302300
) -> Self {
303301
let mut this_adc = Self {
@@ -323,10 +321,10 @@ macro_rules! adc_hal {
323321
this_adc
324322
}
325323

326-
/// Software can use CKMODE::SYNCDIV1 only if
324+
/// Software can use CkMode::SYNCDIV1 only if
327325
/// hclk and sysclk are the same. (see reference manual 15.3.3)
328326
fn clocks_welldefined(&self, clocks: Clocks) -> bool {
329-
if (self.ckmode == CKMODE::SYNCDIV1)
327+
if (self.ckmode == CkMode::SYNCDIV1)
330328
{
331329
clocks.hclk().0 == clocks.sysclk().0
332330
} else {
@@ -355,7 +353,7 @@ macro_rules! adc_hal {
355353
}
356354

357355
fn set_align(&self, align: Align) {
358-
self.rb.cfgr.modify(|_, w| w.align().bit(align.bitvalue()));
356+
self.rb.cfgr.modify(|_, w| w.align().variant(align.into()));
359357
}
360358

361359
fn enable(&mut self) {
@@ -367,7 +365,6 @@ macro_rules! adc_hal {
367365
self.rb.cr.modify(|_, w| w.aden().clear_bit());
368366
}
369367

370-
371368
/// Calibrate according to 15.3.8 in the Reference Manual
372369
fn calibrate(&mut self) {
373370
if !self.rb.cr.read().advregen().is_enabled() {
@@ -384,7 +381,6 @@ macro_rules! adc_hal {
384381
while !self.rb.cr.read().adcal().is_complete() {}
385382
}
386383

387-
388384
fn wait_adc_clk_cycles(&self, cycles: u32) {
389385
let adc_clk_cycle = self.clocks.hclk().0 / (self.ckmode as u32);
390386
asm::delay(adc_clk_cycle * cycles);

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