dma: Fix compiler fence on Transfer stop

The ordering previously used here (Acquire) was not strong enough, since
it only prevents memory reads after the fence to be moved before the
last read before the fence. We want to prevent moving before the last
*write* before the fence (the one that disables DMA). The SeqCst
ordering does that for us.

Author: teskje

src/dma.rs

@@ -146,7 +146,7 @@ impl<B, C: Channel, T> TransferInner<B, C, T> {
     /// Stop this transfer
     fn stop(&mut self) {
         self.channel.disable();
-        atomic::compiler_fence(Ordering::Acquire);
+        atomic::compiler_fence(Ordering::SeqCst);
     }
 }