@@ -103,9 +103,9 @@ mod usb_clocking {
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use crate :: stm32:: rcc:: cfgr;
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pub ( crate ) fn is_valid (
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- _sysclk : & u32 ,
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- _hse : & Option < u32 > ,
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- _pclk1 : & u32 ,
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+ _sysclk : u32 ,
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+ _hse : Option < u32 > ,
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+ _pclk1 : u32 ,
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_pll_config : & Option < PllConfig > ,
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) -> ( bool , bool ) {
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( false , false )
@@ -132,9 +132,9 @@ mod usb_clocking {
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/// Check for all clock options to be
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pub ( crate ) fn is_valid (
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- sysclk : & u32 ,
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- hse : & Option < u32 > ,
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- pclk1 : & u32 ,
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+ sysclk : u32 ,
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+ hse : Option < u32 > ,
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+ pclk1 : u32 ,
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pll_config : & Option < PllConfig > ,
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) -> ( cfgr:: USBPRE_A , bool ) {
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// the USB clock is only valid if an external crystal is used, the PLL is enabled, and the
@@ -143,7 +143,7 @@ mod usb_clocking {
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let usb_ok = hse. is_some ( ) && pll_config. is_some ( ) ;
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// The APB1 clock must have a minimum frequency of 10 MHz to avoid data overrun/underrun
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// problems. [RM0316 32.5.2]
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- if * pclk1 >= 10_000_000 {
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+ if pclk1 >= 10_000_000 {
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match ( usb_ok, sysclk) {
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( true , 72_000_000 ) => ( cfgr:: USBPRE_A :: DIV1_5 , true ) ,
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( true , 48_000_000 ) => ( cfgr:: USBPRE_A :: DIV1 , true ) ,
@@ -537,8 +537,7 @@ impl CFGR {
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} )
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}
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- let ( usbpre, usbclk_valid) =
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- usb_clocking:: is_valid ( & sysclk, & self . hse , & pclk1, & pll_config) ;
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+ let ( usbpre, usbclk_valid) = usb_clocking:: is_valid ( sysclk, self . hse , pclk1, & pll_config) ;
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let rcc = unsafe { & * RCC :: ptr ( ) } ;
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