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Sh3Rm4nSh3Rm4n
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Use cfgr and cfgr2 globally
1 parent f0c14b2 commit 022155b

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‎src/rcc.rs

Lines changed: 47 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
//! Reset and Clock Control
22
33
use crate::stm32::{
4-
rcc::{self, cfgr},
4+
rcc::{self, cfgr, cfgr2},
55
RCC,
66
};
77

@@ -169,9 +169,9 @@ pub struct CFGR {
169169
}
170170

171171
pub(crate) struct PllConfig {
172-
src: rcc::cfgr::PLLSRC_A,
173-
mul: rcc::cfgr::PLLMUL_A,
174-
div: Option<rcc::cfgr2::PREDIV_A>,
172+
src: cfgr::PLLSRC_A,
173+
mul: cfgr::PLLMUL_A,
174+
div: Option<cfgr2::PREDIV_A>,
175175
}
176176

177177
/// Determine the [greatest common divisor](https://en.wikipedia.org/wiki/Greatest_common_divisor)
@@ -187,46 +187,46 @@ fn gcd(mut a: u32, mut b: u32) -> u32 {
187187
}
188188

189189
/// Convert pll multiplier into equivalent register field type
190-
fn into_pll_mul(mul: u8) -> rcc::cfgr::PLLMUL_A {
190+
fn into_pll_mul(mul: u8) -> cfgr::PLLMUL_A {
191191
match mul {
192-
2 => rcc::cfgr::PLLMUL_A::MUL2,
193-
3 => rcc::cfgr::PLLMUL_A::MUL3,
194-
4 => rcc::cfgr::PLLMUL_A::MUL4,
195-
5 => rcc::cfgr::PLLMUL_A::MUL5,
196-
6 => rcc::cfgr::PLLMUL_A::MUL6,
197-
7 => rcc::cfgr::PLLMUL_A::MUL7,
198-
8 => rcc::cfgr::PLLMUL_A::MUL8,
199-
9 => rcc::cfgr::PLLMUL_A::MUL9,
200-
10 => rcc::cfgr::PLLMUL_A::MUL10,
201-
11 => rcc::cfgr::PLLMUL_A::MUL11,
202-
12 => rcc::cfgr::PLLMUL_A::MUL12,
203-
13 => rcc::cfgr::PLLMUL_A::MUL13,
204-
14 => rcc::cfgr::PLLMUL_A::MUL14,
205-
15 => rcc::cfgr::PLLMUL_A::MUL15,
206-
16 => rcc::cfgr::PLLMUL_A::MUL16,
192+
2 => cfgr::PLLMUL_A::MUL2,
193+
3 => cfgr::PLLMUL_A::MUL3,
194+
4 => cfgr::PLLMUL_A::MUL4,
195+
5 => cfgr::PLLMUL_A::MUL5,
196+
6 => cfgr::PLLMUL_A::MUL6,
197+
7 => cfgr::PLLMUL_A::MUL7,
198+
8 => cfgr::PLLMUL_A::MUL8,
199+
9 => cfgr::PLLMUL_A::MUL9,
200+
10 => cfgr::PLLMUL_A::MUL10,
201+
11 => cfgr::PLLMUL_A::MUL11,
202+
12 => cfgr::PLLMUL_A::MUL12,
203+
13 => cfgr::PLLMUL_A::MUL13,
204+
14 => cfgr::PLLMUL_A::MUL14,
205+
15 => cfgr::PLLMUL_A::MUL15,
206+
16 => cfgr::PLLMUL_A::MUL16,
207207
_ => unreachable!(),
208208
}
209209
}
210210

211211
/// Convert pll divisor into equivalent register field type
212-
fn into_pre_div(div: u8) -> rcc::cfgr2::PREDIV_A {
212+
fn into_pre_div(div: u8) -> cfgr2::PREDIV_A {
213213
match div {
214-
1 => rcc::cfgr2::PREDIV_A::DIV1,
215-
2 => rcc::cfgr2::PREDIV_A::DIV2,
216-
3 => rcc::cfgr2::PREDIV_A::DIV3,
217-
4 => rcc::cfgr2::PREDIV_A::DIV4,
218-
5 => rcc::cfgr2::PREDIV_A::DIV5,
219-
6 => rcc::cfgr2::PREDIV_A::DIV6,
220-
7 => rcc::cfgr2::PREDIV_A::DIV7,
221-
8 => rcc::cfgr2::PREDIV_A::DIV8,
222-
9 => rcc::cfgr2::PREDIV_A::DIV9,
223-
10 => rcc::cfgr2::PREDIV_A::DIV10,
224-
11 => rcc::cfgr2::PREDIV_A::DIV11,
225-
12 => rcc::cfgr2::PREDIV_A::DIV12,
226-
13 => rcc::cfgr2::PREDIV_A::DIV13,
227-
14 => rcc::cfgr2::PREDIV_A::DIV14,
228-
15 => rcc::cfgr2::PREDIV_A::DIV15,
229-
16 => rcc::cfgr2::PREDIV_A::DIV16,
214+
1 => cfgr2::PREDIV_A::DIV1,
215+
2 => cfgr2::PREDIV_A::DIV2,
216+
3 => cfgr2::PREDIV_A::DIV3,
217+
4 => cfgr2::PREDIV_A::DIV4,
218+
5 => cfgr2::PREDIV_A::DIV5,
219+
6 => cfgr2::PREDIV_A::DIV6,
220+
7 => cfgr2::PREDIV_A::DIV7,
221+
8 => cfgr2::PREDIV_A::DIV8,
222+
9 => cfgr2::PREDIV_A::DIV9,
223+
10 => cfgr2::PREDIV_A::DIV10,
224+
11 => cfgr2::PREDIV_A::DIV11,
225+
12 => cfgr2::PREDIV_A::DIV12,
226+
13 => cfgr2::PREDIV_A::DIV13,
227+
14 => cfgr2::PREDIV_A::DIV14,
228+
15 => cfgr2::PREDIV_A::DIV15,
229+
16 => cfgr2::PREDIV_A::DIV16,
230230
_ => unreachable!(),
231231
}
232232
}
@@ -341,7 +341,7 @@ impl CFGR {
341341
assert!(sysclk <= 72_000_000);
342342

343343
let pll_src = if self.hse.is_some() {
344-
rcc::cfgr::PLLSRC_A::HSE_DIV_PREDIV
344+
cfgr::PLLSRC_A::HSE_DIV_PREDIV
345345
} else {
346346
cfgr::PLLSRC_A::HSI_DIV2
347347
};
@@ -412,9 +412,9 @@ impl CFGR {
412412
// Select hardware clock source of the PLL
413413
// TODO Check whether HSI_DIV2 could be useful
414414
let pll_src = if self.hse.is_some() {
415-
rcc::cfgr::PLLSRC_A::HSE_DIV_PREDIV
415+
cfgr::PLLSRC_A::HSE_DIV_PREDIV
416416
} else {
417-
rcc::cfgr::PLLSRC_A::HSI_DIV_PREDIV
417+
cfgr::PLLSRC_A::HSI_DIV_PREDIV
418418
};
419419

420420
// Convert into register bit field types
@@ -436,7 +436,7 @@ impl CFGR {
436436
/// The system clock source is determined by the chosen system clock and the provided hardware
437437
/// clock.
438438
/// This function does only chose the PLL if needed, otherwise it will use the oscillator clock as system clock.
439-
fn get_sysclk(&self) -> (u32, rcc::cfgr::SW_A, Option<PllConfig>) {
439+
fn get_sysclk(&self) -> (u32, cfgr::SW_A, Option<PllConfig>) {
440440
// If a sysclk is given, check if the PLL has to be used,
441441
// else select the system clock source, which is either HSI or HSE.
442442
if let Some(sysclk) = self.sysclk {
@@ -447,32 +447,32 @@ impl CFGR {
447447
// because the two valid USB clocks, 72 Mhz and 48 Mhz, can't be generated
448448
// directly from neither the internal rc (8 Mhz) nor the external
449449
// Oscillator (max 32 Mhz), without using the PLL.
450-
(hseclk, rcc::cfgr::SW_A::HSE, None)
450+
(hseclk, cfgr::SW_A::HSE, None)
451451
} else {
452452
let clock_with_pll = self.calc_pll(sysclk);
453453
(
454454
clock_with_pll.0,
455-
rcc::cfgr::SW_A::PLL,
455+
cfgr::SW_A::PLL,
456456
Some(clock_with_pll.1),
457457
)
458458
}
459459
} else if sysclk == HSI {
460460
// No need to use the PLL
461-
(HSI, rcc::cfgr::SW_A::HSE, None)
461+
(HSI, cfgr::SW_A::HSE, None)
462462
} else {
463463
let clock_with_pll = self.calc_pll(sysclk);
464464
(
465465
clock_with_pll.0,
466-
rcc::cfgr::SW_A::PLL,
466+
cfgr::SW_A::PLL,
467467
Some(clock_with_pll.1),
468468
)
469469
}
470470
} else if let Some(hseclk) = self.hse {
471471
// Use HSE as system clock
472-
(hseclk, rcc::cfgr::SW_A::HSE, None)
472+
(hseclk, cfgr::SW_A::HSE, None)
473473
} else {
474474
// Use HSI as system clock
475-
(HSI, rcc::cfgr::SW_A::HSI, None)
475+
(HSI, cfgr::SW_A::HSI, None)
476476
}
477477
}
478478

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