From 8ca05433c328b6a690a0cfc7da3aec4031dbcd21 Mon Sep 17 00:00:00 2001 From: Johnny Egeland Date: Fri, 4 Dec 2020 13:35:08 +0100 Subject: [PATCH 01/12] Added support for OpenDrain configuration on Sck and Mosi SPI pins. --- src/spi.rs | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/spi.rs b/src/spi.rs index 234316a0..b4a798f7 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -3,6 +3,8 @@ To construct the SPI instances, use the `Spi::spiX` functions. The pin parameter is a tuple containing `(sck, miso, mosi)` which should be configured as `(Alternate, Input, Alternate)`. + As some STM32F1xx chips have 5V tolerant SPI pins, it is also possible to configure Sck and Mosi outputs as `Alternate`. Then + a simple Pull-Up to 5V can be used to use SPI on a 5V bus without a level shifter. You can also use `NoSck`, `NoMiso` or `NoMosi` if you don't want to use the pins @@ -135,8 +137,10 @@ macro_rules! remap { const REMAP: bool = $state; } impl Sck<$name> for $SCK> {} + impl Sck<$name> for $SCK> {} impl Miso<$name> for $MISO> {} impl Mosi<$name> for $MOSI> {} + impl Mosi<$name> for $MOSI> {} }; } From 3c1c7cd989633be30d7df834ea375c964f907776 Mon Sep 17 00:00:00 2001 From: Johnny Egeland Date: Fri, 4 Dec 2020 13:36:29 +0100 Subject: [PATCH 02/12] Added missing use for OpenDrain --- src/spi.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/spi.rs b/src/spi.rs index b4a798f7..bf772b90 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -50,7 +50,7 @@ use crate::gpio::gpioa::{PA5, PA6, PA7}; use crate::gpio::gpiob::{PB13, PB14, PB15, PB3, PB4, PB5}; #[cfg(feature = "connectivity")] use crate::gpio::gpioc::{PC10, PC11, PC12}; -use crate::gpio::{Alternate, Floating, Input, PushPull}; +use crate::gpio::{Alternate, Floating, Input, PushPull, OpenDrain}; use crate::rcc::{Clocks, Enable, GetBusFreq, Reset, APB1, APB2}; use crate::time::Hertz; From 76d6889e16606a13b4259f37a225818fc1beb9f5 Mon Sep 17 00:00:00 2001 From: Johnny Egeland Date: Fri, 4 Dec 2020 13:42:43 +0100 Subject: [PATCH 03/12] Changes formatting to please the format checker. --- src/spi.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/spi.rs b/src/spi.rs index bf772b90..c2ffb19a 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -50,7 +50,7 @@ use crate::gpio::gpioa::{PA5, PA6, PA7}; use crate::gpio::gpiob::{PB13, PB14, PB15, PB3, PB4, PB5}; #[cfg(feature = "connectivity")] use crate::gpio::gpioc::{PC10, PC11, PC12}; -use crate::gpio::{Alternate, Floating, Input, PushPull, OpenDrain}; +use crate::gpio::{Alternate, Floating, Input, OpenDrain, PushPull}; use crate::rcc::{Clocks, Enable, GetBusFreq, Reset, APB1, APB2}; use crate::time::Hertz; From 1769cb52e83d2b87c18b162b9223c6e75efeff14 Mon Sep 17 00:00:00 2001 From: Johnny Egeland Date: Fri, 4 Dec 2020 21:45:19 +0100 Subject: [PATCH 04/12] Re-introduced trait for defining the wait and is_done functions --- examples/spi-dma.rs | 3 ++- src/dma.rs | 33 ++++++++++++++++++++++++++------- 2 files changed, 28 insertions(+), 8 deletions(-) diff --git a/examples/spi-dma.rs b/examples/spi-dma.rs index d22c8cde..32806ecf 100644 --- a/examples/spi-dma.rs +++ b/examples/spi-dma.rs @@ -11,6 +11,7 @@ use stm32f1xx_hal::{ pac, prelude::*, spi::{Mode, Phase, Polarity, Spi}, + dma::{TransferOperation} }; #[entry] @@ -49,7 +50,7 @@ fn main() -> ! { let spi_dma = spi.with_tx_dma(dma.5); // Start a DMA transfer - let transfer = spi_dma.write(b"hello, world"); + let mut transfer = spi_dma.write(b"hello, world"); // Wait for it to finnish. The transfer takes ownership over the SPI device // and the data being sent anb those things are returned by transfer.wait diff --git a/src/dma.rs b/src/dma.rs index b999fc28..df3185ad 100644 --- a/src/dma.rs +++ b/src/dma.rs @@ -60,6 +60,25 @@ pub trait TransferPayload { fn stop(&mut self); } +/// Trait implemented by `Transfer` to provide access to the DMA Transfer Operation. +/// The Trait defines methods for checking if the operation is complete, or waiting for +/// the operation to complete. The wait function is also used to return ownership of the +/// transmission buffer and `TransferPayload` (An RxDma or TxDma wrapping a peripheral). +pub trait TransferOperation +{ + /// Checks if a Transmission is complete + fn is_done(&self) -> bool; + + /// Wait for transmission to complete + /// + /// When the transmission is complete, the ownership of the buffer and the "Payload" + /// (the instance that started the Transfer) is returned to the caller. + /// + /// # Returns + /// - Tuple containing the Transmitted buffer and the Payload (the instance initiating the transfer) + fn wait(self) -> (BUFFER, DMA); +} + pub struct Transfer where PAYLOAD: TransferPayload, @@ -128,7 +147,7 @@ macro_rules! dma { use crate::pac::{$DMAX, dma1}; - use crate::dma::{CircBuffer, DmaExt, Error, Event, Half, Transfer, W, RxDma, TxDma, TransferPayload}; + use crate::dma::{CircBuffer, DmaExt, Error, Event, Half, Transfer, W, RxDma, TxDma, TransferOperation, TransferPayload}; use crate::rcc::{AHB, Enable}; #[allow(clippy::manual_non_exhaustive)] @@ -295,15 +314,15 @@ macro_rules! dma { } } - impl Transfer> + impl TransferOperation> for Transfer> where RxDma: TransferPayload, { - pub fn is_done(&self) -> bool { + fn is_done(&self) -> bool { !self.payload.channel.in_progress() } - pub fn wait(mut self) -> (BUFFER, RxDma) { + fn wait(mut self) -> (BUFFER, RxDma) { while !self.is_done() {} atomic::compiler_fence(Ordering::Acquire); @@ -333,15 +352,15 @@ macro_rules! dma { } } - impl Transfer> + impl TransferOperation> for Transfer> where TxDma: TransferPayload, { - pub fn is_done(&self) -> bool { + fn is_done(&self) -> bool { !self.payload.channel.in_progress() } - pub fn wait(mut self) -> (BUFFER, TxDma) { + fn wait(mut self) -> (BUFFER, TxDma) { while !self.is_done() {} atomic::compiler_fence(Ordering::Acquire); From a20bdaa6c378d745a42c939edb00bbb973e62e0d Mon Sep 17 00:00:00 2001 From: Johnny Egeland Date: Fri, 4 Dec 2020 22:16:41 +0100 Subject: [PATCH 05/12] Working on example --- examples/spi-dma.rs | 58 ++++++++++++++++++++++++++++++++++++++------- src/dma.rs | 8 +++---- 2 files changed, 53 insertions(+), 13 deletions(-) diff --git a/examples/spi-dma.rs b/examples/spi-dma.rs index 32806ecf..f2f27fbc 100644 --- a/examples/spi-dma.rs +++ b/examples/spi-dma.rs @@ -6,14 +6,18 @@ */ use panic_halt as _; +use cortex_m::singleton; use cortex_m_rt::entry; use stm32f1xx_hal::{ pac, prelude::*, - spi::{Mode, Phase, Polarity, Spi}, - dma::{TransferOperation} + spi::{Mode, Phase, Polarity, Spi, SpiTxDma}, + dma::{R, Transfer, Transferable, WriteDma} }; +// Set size of data buffer to transmit via SPI DMA +const DATA_BUFFER_SIZE: usize = 8; + #[entry] fn main() -> ! { // Get access to the device specific peripherals from the peripheral access crate @@ -47,14 +51,50 @@ fn main() -> ! { let dma = dp.DMA1.split(&mut rcc.ahb); // Connect the SPI device to the DMA - let spi_dma = spi.with_tx_dma(dma.5); + let mut spi_dma = spi.with_tx_dma(dma.5); + + // Create a mutable data buffer, as we need to write data into it + let data_buffer: &'static mut [u8; DATA_BUFFER_SIZE] = + singleton!(: [u8; DATA_BUFFER_SIZE] = [0; DATA_BUFFER_SIZE]).unwrap(); + + // Use a byte counter to generate some data for our buffer + let mut data_byte = 0u8; + + + // Do SPI transmission in an endless loop + loop { + // Fill the buffer with some data + for ix in 0..DATA_BUFFER_SIZE { + // Increase by 1, and insure it wraps + data_byte = data_byte.wrapping_add(1u8); - // Start a DMA transfer - let mut transfer = spi_dma.write(b"hello, world"); + // Put the byte into the buffer + data_buffer[ix] = data_byte; + } - // Wait for it to finnish. The transfer takes ownership over the SPI device - // and the data being sent anb those things are returned by transfer.wait - let (_buffer, _spi_dma) = transfer.wait(); + // Call write function + let transfer = write_spi_dma(spi_dma, data_buffer); + + // Wait for transfer to complete + let (ret_buffer, ret_spidma) = transfer.wait(); + + // Return ownership, so we can re-use these the next iteration + data_buffer = ret_buffer; + spi_dma = ret_spidma; + } +} - loop {} +/// The writing is done is a separate function, as this is typically how a driver would work +/// The Driver will take ownership of the SPI DMA for the duration of the Transfer Operation. +/// When complete, the wait() function returns the ownership of the buffer and SPI DMA, which +/// makes it usabe for something else. This way, one SPI can be shared among multiple drivers. +fn write_spi_dma(spi_dma: SpiTxDma, buffer: &'static mut [u8]) + -> Transfer> +where + SpiTxDma: WriteDma<&'static mut [u8], u8>, + Transfer>: + Transferable<&'static mut [u8], SpiTxDma> +{ + // Simply call write, and return the Transfer instance + spi_dma.write(buffer) } diff --git a/src/dma.rs b/src/dma.rs index df3185ad..b18e7bff 100644 --- a/src/dma.rs +++ b/src/dma.rs @@ -64,7 +64,7 @@ pub trait TransferPayload { /// The Trait defines methods for checking if the operation is complete, or waiting for /// the operation to complete. The wait function is also used to return ownership of the /// transmission buffer and `TransferPayload` (An RxDma or TxDma wrapping a peripheral). -pub trait TransferOperation +pub trait Transferable { /// Checks if a Transmission is complete fn is_done(&self) -> bool; @@ -147,7 +147,7 @@ macro_rules! dma { use crate::pac::{$DMAX, dma1}; - use crate::dma::{CircBuffer, DmaExt, Error, Event, Half, Transfer, W, RxDma, TxDma, TransferOperation, TransferPayload}; + use crate::dma::{CircBuffer, DmaExt, Error, Event, Half, Transfer, W, RxDma, TxDma, Transferable, TransferPayload}; use crate::rcc::{AHB, Enable}; #[allow(clippy::manual_non_exhaustive)] @@ -314,7 +314,7 @@ macro_rules! dma { } } - impl TransferOperation> for Transfer> + impl Transferable> for Transfer> where RxDma: TransferPayload, { @@ -352,7 +352,7 @@ macro_rules! dma { } } - impl TransferOperation> for Transfer> + impl Transferable> for Transfer> where TxDma: TransferPayload, { From 37bf8fb79da78d5f1dc6fb4fa26083d372485f2c Mon Sep 17 00:00:00 2001 From: Johnny Egeland Date: Fri, 4 Dec 2020 22:19:34 +0100 Subject: [PATCH 06/12] Updated example to showcase the use of abstractions for SPI DMA transfers. Also added dynamically generated data, and transmission in a continuous loop. --- examples/spi-dma.rs | 15 ++++++++------- src/dma.rs | 9 ++++----- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/examples/spi-dma.rs b/examples/spi-dma.rs index f2f27fbc..b1b84f4d 100644 --- a/examples/spi-dma.rs +++ b/examples/spi-dma.rs @@ -9,10 +9,10 @@ use panic_halt as _; use cortex_m::singleton; use cortex_m_rt::entry; use stm32f1xx_hal::{ + dma::{Transfer, Transferable, WriteDma, R}, pac, prelude::*, spi::{Mode, Phase, Polarity, Spi, SpiTxDma}, - dma::{R, Transfer, Transferable, WriteDma} }; // Set size of data buffer to transmit via SPI DMA @@ -54,12 +54,11 @@ fn main() -> ! { let mut spi_dma = spi.with_tx_dma(dma.5); // Create a mutable data buffer, as we need to write data into it - let data_buffer: &'static mut [u8; DATA_BUFFER_SIZE] = - singleton!(: [u8; DATA_BUFFER_SIZE] = [0; DATA_BUFFER_SIZE]).unwrap(); + let mut data_buffer: &'static mut [u8] = + singleton!(: [u8; DATA_BUFFER_SIZE] = [0; DATA_BUFFER_SIZE]).unwrap(); // Use a byte counter to generate some data for our buffer let mut data_byte = 0u8; - // Do SPI transmission in an endless loop loop { @@ -88,12 +87,14 @@ fn main() -> ! { /// The Driver will take ownership of the SPI DMA for the duration of the Transfer Operation. /// When complete, the wait() function returns the ownership of the buffer and SPI DMA, which /// makes it usabe for something else. This way, one SPI can be shared among multiple drivers. -fn write_spi_dma(spi_dma: SpiTxDma, buffer: &'static mut [u8]) - -> Transfer> +fn write_spi_dma( + spi_dma: SpiTxDma, + buffer: &'static mut [u8], +) -> Transfer> where SpiTxDma: WriteDma<&'static mut [u8], u8>, Transfer>: - Transferable<&'static mut [u8], SpiTxDma> + Transferable<&'static mut [u8], SpiTxDma>, { // Simply call write, and return the Transfer instance spi_dma.write(buffer) diff --git a/src/dma.rs b/src/dma.rs index b18e7bff..845b6150 100644 --- a/src/dma.rs +++ b/src/dma.rs @@ -64,16 +64,15 @@ pub trait TransferPayload { /// The Trait defines methods for checking if the operation is complete, or waiting for /// the operation to complete. The wait function is also used to return ownership of the /// transmission buffer and `TransferPayload` (An RxDma or TxDma wrapping a peripheral). -pub trait Transferable -{ +pub trait Transferable { /// Checks if a Transmission is complete fn is_done(&self) -> bool; /// Wait for transmission to complete - /// - /// When the transmission is complete, the ownership of the buffer and the "Payload" + /// + /// When the transmission is complete, the ownership of the buffer and the "Payload" /// (the instance that started the Transfer) is returned to the caller. - /// + /// /// # Returns /// - Tuple containing the Transmitted buffer and the Payload (the instance initiating the transfer) fn wait(self) -> (BUFFER, DMA); From ca26026b889d62f0ff451c7f870cfda2fb06fc94 Mon Sep 17 00:00:00 2001 From: Johnny Egeland Date: Fri, 4 Dec 2020 22:47:18 +0100 Subject: [PATCH 07/12] Re-instated the old simple SPI DMA example, and added a new example for use via abstraction. --- examples/spi-dma-abstract.rs | 101 +++++++++++++++++++++++++++++++++++ examples/spi-dma.rs | 59 ++++---------------- 2 files changed, 110 insertions(+), 50 deletions(-) create mode 100644 examples/spi-dma-abstract.rs diff --git a/examples/spi-dma-abstract.rs b/examples/spi-dma-abstract.rs new file mode 100644 index 00000000..b1b84f4d --- /dev/null +++ b/examples/spi-dma-abstract.rs @@ -0,0 +1,101 @@ +#![no_std] +#![no_main] + +/** + Transmits data over an SPI port using DMA +*/ +use panic_halt as _; + +use cortex_m::singleton; +use cortex_m_rt::entry; +use stm32f1xx_hal::{ + dma::{Transfer, Transferable, WriteDma, R}, + pac, + prelude::*, + spi::{Mode, Phase, Polarity, Spi, SpiTxDma}, +}; + +// Set size of data buffer to transmit via SPI DMA +const DATA_BUFFER_SIZE: usize = 8; + +#[entry] +fn main() -> ! { + // Get access to the device specific peripherals from the peripheral access crate + let dp = pac::Peripherals::take().unwrap(); + + // Take ownership over the raw flash and rcc devices and convert them into the corresponding + // HAL structs + let mut flash = dp.FLASH.constrain(); + let mut rcc = dp.RCC.constrain(); + + // Freeze the configuration of all the clocks in the system and store the frozen frequencies in + // `clocks` + let clocks = rcc.cfgr.freeze(&mut flash.acr); + + // Acquire the GPIOA peripheral + let mut gpiob = dp.GPIOB.split(&mut rcc.apb2); + + let pins = ( + gpiob.pb13.into_alternate_push_pull(&mut gpiob.crh), + gpiob.pb14.into_floating_input(&mut gpiob.crh), + gpiob.pb15.into_alternate_push_pull(&mut gpiob.crh), + ); + + let spi_mode = Mode { + polarity: Polarity::IdleLow, + phase: Phase::CaptureOnFirstTransition, + }; + let spi = Spi::spi2(dp.SPI2, pins, spi_mode, 100.khz(), clocks, &mut rcc.apb1); + + // Set up the DMA device + let dma = dp.DMA1.split(&mut rcc.ahb); + + // Connect the SPI device to the DMA + let mut spi_dma = spi.with_tx_dma(dma.5); + + // Create a mutable data buffer, as we need to write data into it + let mut data_buffer: &'static mut [u8] = + singleton!(: [u8; DATA_BUFFER_SIZE] = [0; DATA_BUFFER_SIZE]).unwrap(); + + // Use a byte counter to generate some data for our buffer + let mut data_byte = 0u8; + + // Do SPI transmission in an endless loop + loop { + // Fill the buffer with some data + for ix in 0..DATA_BUFFER_SIZE { + // Increase by 1, and insure it wraps + data_byte = data_byte.wrapping_add(1u8); + + // Put the byte into the buffer + data_buffer[ix] = data_byte; + } + + // Call write function + let transfer = write_spi_dma(spi_dma, data_buffer); + + // Wait for transfer to complete + let (ret_buffer, ret_spidma) = transfer.wait(); + + // Return ownership, so we can re-use these the next iteration + data_buffer = ret_buffer; + spi_dma = ret_spidma; + } +} + +/// The writing is done is a separate function, as this is typically how a driver would work +/// The Driver will take ownership of the SPI DMA for the duration of the Transfer Operation. +/// When complete, the wait() function returns the ownership of the buffer and SPI DMA, which +/// makes it usabe for something else. This way, one SPI can be shared among multiple drivers. +fn write_spi_dma( + spi_dma: SpiTxDma, + buffer: &'static mut [u8], +) -> Transfer> +where + SpiTxDma: WriteDma<&'static mut [u8], u8>, + Transfer>: + Transferable<&'static mut [u8], SpiTxDma>, +{ + // Simply call write, and return the Transfer instance + spi_dma.write(buffer) +} diff --git a/examples/spi-dma.rs b/examples/spi-dma.rs index b1b84f4d..5a8957e5 100644 --- a/examples/spi-dma.rs +++ b/examples/spi-dma.rs @@ -6,18 +6,14 @@ */ use panic_halt as _; -use cortex_m::singleton; use cortex_m_rt::entry; use stm32f1xx_hal::{ - dma::{Transfer, Transferable, WriteDma, R}, pac, prelude::*, - spi::{Mode, Phase, Polarity, Spi, SpiTxDma}, + spi::{Mode, Phase, Polarity, Spi}, + dma::Transferable }; -// Set size of data buffer to transmit via SPI DMA -const DATA_BUFFER_SIZE: usize = 8; - #[entry] fn main() -> ! { // Get access to the device specific peripherals from the peripheral access crate @@ -51,51 +47,14 @@ fn main() -> ! { let dma = dp.DMA1.split(&mut rcc.ahb); // Connect the SPI device to the DMA - let mut spi_dma = spi.with_tx_dma(dma.5); - - // Create a mutable data buffer, as we need to write data into it - let mut data_buffer: &'static mut [u8] = - singleton!(: [u8; DATA_BUFFER_SIZE] = [0; DATA_BUFFER_SIZE]).unwrap(); - - // Use a byte counter to generate some data for our buffer - let mut data_byte = 0u8; - - // Do SPI transmission in an endless loop - loop { - // Fill the buffer with some data - for ix in 0..DATA_BUFFER_SIZE { - // Increase by 1, and insure it wraps - data_byte = data_byte.wrapping_add(1u8); + let spi_dma = spi.with_tx_dma(dma.5); - // Put the byte into the buffer - data_buffer[ix] = data_byte; - } + // Start a DMA transfer + let transfer = spi_dma.write(b"hello, world"); - // Call write function - let transfer = write_spi_dma(spi_dma, data_buffer); - - // Wait for transfer to complete - let (ret_buffer, ret_spidma) = transfer.wait(); - - // Return ownership, so we can re-use these the next iteration - data_buffer = ret_buffer; - spi_dma = ret_spidma; - } -} + // Wait for it to finnish. The transfer takes ownership over the SPI device + // and the data being sent anb those things are returned by transfer.wait + let (_buffer, _spi_dma) = transfer.wait(); -/// The writing is done is a separate function, as this is typically how a driver would work -/// The Driver will take ownership of the SPI DMA for the duration of the Transfer Operation. -/// When complete, the wait() function returns the ownership of the buffer and SPI DMA, which -/// makes it usabe for something else. This way, one SPI can be shared among multiple drivers. -fn write_spi_dma( - spi_dma: SpiTxDma, - buffer: &'static mut [u8], -) -> Transfer> -where - SpiTxDma: WriteDma<&'static mut [u8], u8>, - Transfer>: - Transferable<&'static mut [u8], SpiTxDma>, -{ - // Simply call write, and return the Transfer instance - spi_dma.write(buffer) + loop {} } From 16e219f61fadea1ccf0a209430477c35d514ed26 Mon Sep 17 00:00:00 2001 From: Johnny Egeland Date: Fri, 4 Dec 2020 22:50:27 +0100 Subject: [PATCH 08/12] Fixed formatting problem --- examples/spi-dma.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/spi-dma.rs b/examples/spi-dma.rs index 5a8957e5..da29aab5 100644 --- a/examples/spi-dma.rs +++ b/examples/spi-dma.rs @@ -8,10 +8,10 @@ use panic_halt as _; use cortex_m_rt::entry; use stm32f1xx_hal::{ + dma::Transferable, pac, prelude::*, spi::{Mode, Phase, Polarity, Spi}, - dma::Transferable }; #[entry] From d09489c8f69ba3c8bf8b36ed74352146c7881e0a Mon Sep 17 00:00:00 2001 From: Johnny Egeland Date: Fri, 4 Dec 2020 22:56:58 +0100 Subject: [PATCH 09/12] Added missing trait after re-introducting it into the DMA. --- examples/adc-dma-rx.rs | 2 +- examples/serial-dma-rx.rs | 1 + examples/serial-dma-tx.rs | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/examples/adc-dma-rx.rs b/examples/adc-dma-rx.rs index be62425e..59109433 100644 --- a/examples/adc-dma-rx.rs +++ b/examples/adc-dma-rx.rs @@ -8,7 +8,7 @@ use panic_halt as _; use cortex_m::{asm, singleton}; use cortex_m_rt::entry; -use stm32f1xx_hal::{adc, pac, prelude::*}; +use stm32f1xx_hal::{adc, dma::Transferable, pac, prelude::*}; #[entry] fn main() -> ! { diff --git a/examples/serial-dma-rx.rs b/examples/serial-dma-rx.rs index 1fb33610..7869d2a7 100644 --- a/examples/serial-dma-rx.rs +++ b/examples/serial-dma-rx.rs @@ -10,6 +10,7 @@ use cortex_m::{asm, singleton}; use cortex_m_rt::entry; use stm32f1xx_hal::{ + dma::Transferable, pac, prelude::*, serial::{Config, Serial}, diff --git a/examples/serial-dma-tx.rs b/examples/serial-dma-tx.rs index 98c5fc2d..b334f6a5 100644 --- a/examples/serial-dma-tx.rs +++ b/examples/serial-dma-tx.rs @@ -10,6 +10,7 @@ use cortex_m::asm; use cortex_m_rt::entry; use stm32f1xx_hal::{ + dma::Transferable, pac, prelude::*, serial::{Config, Serial}, From f3579cca6c75c3fa2ee55040707a391a801a6f34 Mon Sep 17 00:00:00 2001 From: Johnny Egeland Date: Fri, 4 Dec 2020 23:00:45 +0100 Subject: [PATCH 10/12] Added another missing Transferable use statement --- examples/serial-dma-peek.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/examples/serial-dma-peek.rs b/examples/serial-dma-peek.rs index a4590636..a0f5b946 100644 --- a/examples/serial-dma-peek.rs +++ b/examples/serial-dma-peek.rs @@ -10,6 +10,7 @@ use cortex_m::{asm, singleton}; use cortex_m_rt::entry; use stm32f1xx_hal::{ + dma::Transferable, pac, prelude::*, serial::{Config, Serial}, From b185badd875f5b2debe7ad693b05f3cc337ae810 Mon Sep 17 00:00:00 2001 From: Johnny Egeland Date: Sun, 6 Dec 2020 19:37:26 +0100 Subject: [PATCH 11/12] Added Transferable to the prelude includes, making it unecessary to specify it explicitly in examples. This means all examples are as they where before re-adding the trait. --- examples/adc-dma-rx.rs | 2 +- examples/serial-dma-peek.rs | 1 - examples/serial-dma-rx.rs | 1 - examples/serial-dma-tx.rs | 1 - examples/spi-dma.rs | 1 - src/prelude.rs | 1 + 6 files changed, 2 insertions(+), 5 deletions(-) diff --git a/examples/adc-dma-rx.rs b/examples/adc-dma-rx.rs index 59109433..be62425e 100644 --- a/examples/adc-dma-rx.rs +++ b/examples/adc-dma-rx.rs @@ -8,7 +8,7 @@ use panic_halt as _; use cortex_m::{asm, singleton}; use cortex_m_rt::entry; -use stm32f1xx_hal::{adc, dma::Transferable, pac, prelude::*}; +use stm32f1xx_hal::{adc, pac, prelude::*}; #[entry] fn main() -> ! { diff --git a/examples/serial-dma-peek.rs b/examples/serial-dma-peek.rs index a0f5b946..a4590636 100644 --- a/examples/serial-dma-peek.rs +++ b/examples/serial-dma-peek.rs @@ -10,7 +10,6 @@ use cortex_m::{asm, singleton}; use cortex_m_rt::entry; use stm32f1xx_hal::{ - dma::Transferable, pac, prelude::*, serial::{Config, Serial}, diff --git a/examples/serial-dma-rx.rs b/examples/serial-dma-rx.rs index 7869d2a7..1fb33610 100644 --- a/examples/serial-dma-rx.rs +++ b/examples/serial-dma-rx.rs @@ -10,7 +10,6 @@ use cortex_m::{asm, singleton}; use cortex_m_rt::entry; use stm32f1xx_hal::{ - dma::Transferable, pac, prelude::*, serial::{Config, Serial}, diff --git a/examples/serial-dma-tx.rs b/examples/serial-dma-tx.rs index b334f6a5..98c5fc2d 100644 --- a/examples/serial-dma-tx.rs +++ b/examples/serial-dma-tx.rs @@ -10,7 +10,6 @@ use cortex_m::asm; use cortex_m_rt::entry; use stm32f1xx_hal::{ - dma::Transferable, pac, prelude::*, serial::{Config, Serial}, diff --git a/examples/spi-dma.rs b/examples/spi-dma.rs index da29aab5..d22c8cde 100644 --- a/examples/spi-dma.rs +++ b/examples/spi-dma.rs @@ -8,7 +8,6 @@ use panic_halt as _; use cortex_m_rt::entry; use stm32f1xx_hal::{ - dma::Transferable, pac, prelude::*, spi::{Mode, Phase, Polarity, Spi}, diff --git a/src/prelude.rs b/src/prelude.rs index ff349473..2cdc5aa1 100644 --- a/src/prelude.rs +++ b/src/prelude.rs @@ -4,6 +4,7 @@ pub use crate::crc::CrcExt as _stm32_hal_crc_CrcExt; pub use crate::dma::CircReadDma as _stm32_hal_dma_CircReadDma; pub use crate::dma::DmaExt as _stm32_hal_dma_DmaExt; pub use crate::dma::ReadDma as _stm32_hal_dma_ReadDma; +pub use crate::dma::Transferable as _stm32_hal_dma_Transferable; pub use crate::dma::WriteDma as _stm32_hal_dma_WriteDma; pub use crate::flash::FlashExt as _stm32_hal_flash_FlashExt; pub use crate::gpio::GpioExt as _stm32_hal_gpio_GpioExt; From e66bd1ef0ed694a693d715c07e5178f970ff041a Mon Sep 17 00:00:00 2001 From: Johnny Egeland Date: Sat, 16 Jan 2021 23:20:08 +0100 Subject: [PATCH 12/12] Added changelog entry --- CHANGELOG.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index a1d087e9..dfb259df 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ## [Unreleased] +### Added + +- Reintroduced the "Transferable" trait to make it possible to pass an abstract reference for any SPI DMA. + ## [v0.7.0]- 2020-10-17 ### Breaking changes