@@ -20,6 +20,37 @@ use crate::afio::MAPR;
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use crate :: pwm_input:: Pins ;
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use crate :: timer:: { sealed:: Remap , Timer } ;
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+ /// SMS (Slave Mode Selection) register
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+ pub enum SlaveMode {
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+ /// Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.
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+ EncoderMode1 = 0b001 ,
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+ /// Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.
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+ EncoderMode2 = 0b010 ,
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+ /// Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the
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+ /// level of the other input.
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+ EncoderMode3 = 0b011 ,
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+ /// Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and
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+ /// generates an update of the registers.
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+ ResetMode = 0b100 ,
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+ /// Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
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+ /// reset). Only the start of the counter is controlled.
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+ TriggerMode = 0b110 ,
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+ /// External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
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+ ExternalClockMode1 = 0b111 ,
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+ }
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+
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+ pub struct QeiOptions {
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+ slave_mode : SlaveMode ,
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+ }
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+
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+ impl Default for QeiOptions {
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+ fn default ( ) -> Self {
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+ Self {
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+ slave_mode : SlaveMode :: EncoderMode3 ,
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+ }
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+ }
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+ }
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+
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pub struct Qei < TIM , REMAP , PINS > {
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tim : TIM ,
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pins : PINS ,
@@ -28,63 +59,83 @@ pub struct Qei<TIM, REMAP, PINS> {
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#[ cfg( any( feature = "stm32f100" , feature = "stm32f103" , feature = "stm32f105" , ) ) ]
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impl Timer < TIM1 > {
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- pub fn qei < REMAP , PINS > ( self , pins : PINS , mapr : & mut MAPR ) -> Qei < TIM1 , REMAP , PINS >
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+ pub fn qei < REMAP , PINS > (
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+ self ,
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+ pins : PINS ,
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+ mapr : & mut MAPR ,
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+ options : QeiOptions ,
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+ ) -> Qei < TIM1 , REMAP , PINS >
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where
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REMAP : Remap < Periph = TIM1 > ,
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PINS : Pins < REMAP > ,
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{
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mapr. modify_mapr ( |_, w| unsafe { w. tim1_remap ( ) . bits ( REMAP :: REMAP ) } ) ;
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let Self { tim, clk : _ } = self ;
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- Qei :: _tim1 ( tim, pins)
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+ Qei :: _tim1 ( tim, pins, options )
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}
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}
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impl Timer < TIM2 > {
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- pub fn qei < REMAP , PINS > ( self , pins : PINS , mapr : & mut MAPR ) -> Qei < TIM2 , REMAP , PINS >
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+ pub fn qei < REMAP , PINS > (
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+ self ,
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+ pins : PINS ,
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+ mapr : & mut MAPR ,
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+ options : QeiOptions ,
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+ ) -> Qei < TIM2 , REMAP , PINS >
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where
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REMAP : Remap < Periph = TIM2 > ,
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PINS : Pins < REMAP > ,
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{
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mapr. modify_mapr ( |_, w| unsafe { w. tim2_remap ( ) . bits ( REMAP :: REMAP ) } ) ;
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let Self { tim, clk : _ } = self ;
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- Qei :: _tim2 ( tim, pins)
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+ Qei :: _tim2 ( tim, pins, options )
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}
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}
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impl Timer < TIM3 > {
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- pub fn qei < REMAP , PINS > ( self , pins : PINS , mapr : & mut MAPR ) -> Qei < TIM3 , REMAP , PINS >
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+ pub fn qei < REMAP , PINS > (
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+ self ,
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+ pins : PINS ,
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+ mapr : & mut MAPR ,
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+ options : QeiOptions ,
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+ ) -> Qei < TIM3 , REMAP , PINS >
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where
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REMAP : Remap < Periph = TIM3 > ,
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PINS : Pins < REMAP > ,
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{
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mapr. modify_mapr ( |_, w| unsafe { w. tim3_remap ( ) . bits ( REMAP :: REMAP ) } ) ;
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let Self { tim, clk : _ } = self ;
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- Qei :: _tim3 ( tim, pins)
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+ Qei :: _tim3 ( tim, pins, options )
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}
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}
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#[ cfg( feature = "medium" ) ]
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impl Timer < TIM4 > {
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- pub fn qei < REMAP , PINS > ( self , pins : PINS , mapr : & mut MAPR ) -> Qei < TIM4 , REMAP , PINS >
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+ pub fn qei < REMAP , PINS > (
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+ self ,
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+ pins : PINS ,
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+ mapr : & mut MAPR ,
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+ options : QeiOptions ,
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+ ) -> Qei < TIM4 , REMAP , PINS >
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where
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REMAP : Remap < Periph = TIM4 > ,
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PINS : Pins < REMAP > ,
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{
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mapr. modify_mapr ( |_, w| w. tim4_remap ( ) . bit ( REMAP :: REMAP == 1 ) ) ;
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let Self { tim, clk : _ } = self ;
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- Qei :: _tim4 ( tim, pins)
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+ Qei :: _tim4 ( tim, pins, options )
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}
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}
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macro_rules! hal {
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( $( $TIMX: ident: ( $timX: ident, $timXen: ident, $timXrst: ident) , ) +) => {
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$(
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impl <REMAP , PINS > Qei <$TIMX, REMAP , PINS > {
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- fn $timX( tim: $TIMX, pins: PINS ) -> Self {
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+ fn $timX( tim: $TIMX, pins: PINS , options : QeiOptions ) -> Self {
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// Configure TxC1 and TxC2 as captures
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tim. ccmr1_input( ) . write( |w| w. cc1s( ) . ti1( ) . cc2s( ) . ti2( ) ) ;
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@@ -101,7 +152,7 @@ macro_rules! hal {
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} ) ;
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// configure as quadrature encoder
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- tim. smcr. write( |w| w. sms( ) . bits( 3 ) ) ;
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+ tim. smcr. write( |w| w. sms( ) . bits( options . slave_mode as u8 ) ) ;
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tim. arr. write( |w| w. arr( ) . bits( u16 :: MAX ) ) ;
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tim. cr1. write( |w| w. cen( ) . set_bit( ) ) ;
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