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Commit 9d33a94

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AndreySmirnov81AndreySmirnov81
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rcc: delete rcc param. from Enable and Reset 
1 parent cdc21db commit 9d33a94

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13 files changed

+56
-78
lines changed

13 files changed

+56
-78
lines changed

‎src/adc.rs

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ use core::sync::atomic::{self, Ordering};
1313
use cortex_m::asm::delay;
1414
use embedded_dma::WriteBuffer;
1515

16-
use crate::pac::{self, RCC};
16+
use crate::pac;
1717

1818
/// Continuous mode
1919
pub struct Continuous;
@@ -271,18 +271,15 @@ macro_rules! adc_hal {
271271
}
272272

273273
fn reset(&mut self) {
274-
let rcc = unsafe { &(*RCC::ptr()) };
275-
<$ADC>::reset(rcc);
274+
<$ADC>::reset();
276275
}
277276

278277
fn enable_clock(&mut self) {
279-
let rcc = unsafe { &(*RCC::ptr()) };
280-
<$ADC>::enable(rcc);
278+
<$ADC>::enable();
281279
}
282280

283281
fn disable_clock(&mut self) {
284-
let rcc = unsafe { &(*RCC::ptr()) };
285-
<$ADC>::disable(rcc);
282+
<$ADC>::disable();
286283
}
287284

288285
fn calibrate(&mut self) {

‎src/afio.rs

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
//! # Alternate Function I/Os
2-
use crate::pac::{afio, AFIO, RCC};
2+
use crate::pac::{afio, AFIO};
33

44
use crate::rcc::{Enable, Reset};
55

@@ -13,9 +13,8 @@ pub trait AfioExt {
1313

1414
impl AfioExt for AFIO {
1515
fn constrain(self) -> Parts {
16-
let rcc = unsafe { &(*RCC::ptr()) };
17-
AFIO::enable(rcc);
18-
AFIO::reset(rcc);
16+
AFIO::enable();
17+
AFIO::reset();
1918

2019
Parts {
2120
evcr: EVCR { _0: () },

‎src/can.rs

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@
2121
2222
use crate::afio::MAPR;
2323
use crate::gpio::{self, Alternate, Input};
24-
use crate::pac::{self, RCC};
24+
use crate::pac;
2525

2626
pub trait Pins: crate::Sealed {
2727
type Instance;
@@ -95,17 +95,15 @@ where
9595
/// prevent accidental shared usage.
9696
#[cfg(not(feature = "connectivity"))]
9797
pub fn new(can: Instance, _usb: pac::USB) -> Can<Instance> {
98-
let rcc = unsafe { &(*RCC::ptr()) };
99-
Instance::enable(rcc);
98+
Instance::enable();
10099

101100
Can { _peripheral: can }
102101
}
103102

104103
/// Creates a CAN interaface.
105104
#[cfg(feature = "connectivity")]
106105
pub fn new(can: Instance) -> Can<Instance> {
107-
let rcc = unsafe { &(*RCC::ptr()) };
108-
Instance::enable(rcc);
106+
Instance::enable();
109107

110108
Can { _peripheral: can }
111109
}

‎src/crc.rs

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
//! CRC
22
3-
use crate::pac::{CRC, RCC};
3+
use crate::pac::CRC;
44
use crate::rcc::Enable;
55

66
/// Extension trait to constrain the CRC peripheral
@@ -12,8 +12,7 @@ pub trait CrcExt {
1212

1313
impl CrcExt for CRC {
1414
fn new(self) -> Crc {
15-
let rcc = unsafe { &(*RCC::ptr()) };
16-
CRC::enable(rcc);
15+
CRC::enable();
1716

1817
Crc { crc: self }
1918
}

‎src/dma.rs

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -124,7 +124,7 @@ macro_rules! dma {
124124
pub mod $dmaX {
125125
use core::{sync::atomic::{self, Ordering}, ptr, mem, convert::TryFrom};
126126

127-
use crate::pac::{RCC, $DMAX, dma1};
127+
use crate::pac::{$DMAX, dma1};
128128

129129
use crate::dma::{CircBuffer, DmaExt, Error, Event, Half, Transfer, W, RxDma, TxDma, RxTxDma, TransferPayload};
130130
use crate::rcc::Enable;
@@ -447,8 +447,7 @@ macro_rules! dma {
447447
type Channels = Channels;
448448

449449
fn split(self) -> Channels {
450-
let rcc = unsafe { &(*RCC::ptr()) };
451-
$DMAX::enable(rcc);
450+
$DMAX::enable();
452451

453452
// reset the DMA control registers (stops all on-going transfers)
454453
$(

‎src/gpio.rs

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -340,7 +340,7 @@ macro_rules! gpio {
340340
]) => {
341341
/// GPIO
342342
pub mod $gpiox {
343-
use crate::pac::{$GPIOX, RCC};
343+
use crate::pac::$GPIOX;
344344
use crate::rcc::{Enable, Reset};
345345
use super::{Active, Floating, GpioExt, Input, PartiallyErasedPin, ErasedPin, Pin, Cr};
346346
#[allow(unused)]
@@ -366,9 +366,8 @@ macro_rules! gpio {
366366
type Parts = Parts;
367367

368368
fn split(self) -> Parts {
369-
let rcc = unsafe { &(*RCC::ptr()) };
370-
$GPIOX::enable(rcc);
371-
$GPIOX::reset(rcc);
369+
$GPIOX::enable();
370+
$GPIOX::reset();
372371

373372
Parts {
374373
crl: Cr::<$port_id, false>(()),

‎src/i2c.rs

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
use crate::afio::MAPR;
88
use crate::gpio::{self, Alternate, OpenDrain};
99
use crate::hal::blocking::i2c::{Read, Write, WriteRead};
10-
use crate::pac::{DWT, I2C1, I2C2, RCC};
10+
use crate::pac::{DWT, I2C1, I2C2};
1111
use crate::rcc::{BusClock, Clocks, Enable, Reset};
1212
use crate::time::{kHz, Hertz};
1313
use core::ops::Deref;
@@ -166,9 +166,8 @@ where
166166
/// Configures the I2C peripheral to work in master mode
167167
fn configure<M: Into<Mode>>(i2c: I2C, pins: PINS, mode: M, clocks: Clocks) -> Self {
168168
let mode = mode.into();
169-
let rcc = unsafe { &(*RCC::ptr()) };
170-
I2C::enable(rcc);
171-
I2C::reset(rcc);
169+
I2C::enable();
170+
I2C::reset();
172171

173172
let pclk1 = I2C::clock(&clocks);
174173

‎src/rcc.rs

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -76,8 +76,7 @@ impl APB1 {
7676
impl APB1 {
7777
/// Set power interface clock (PWREN) bit in RCC_APB1ENR
7878
pub fn set_pwren() {
79-
let rcc = unsafe { &*RCC::ptr() };
80-
PWR::enable(rcc);
79+
PWR::enable();
8180
}
8281
}
8382

@@ -309,9 +308,8 @@ impl BKP {
309308
/// Enables write access to the registers in the backup domain
310309
pub fn constrain(self, bkp: crate::pac::BKP, pwr: &mut PWR) -> BackupDomain {
311310
// Enable the backup interface by setting PWREN and BKPEN
312-
let rcc = unsafe { &(*RCC::ptr()) };
313-
crate::pac::BKP::enable(rcc);
314-
crate::pac::PWR::enable(rcc);
311+
crate::pac::BKP::enable();
312+
crate::pac::PWR::enable();
315313

316314
// Enable access to the backup registers
317315
pwr.cr.modify(|_r, w| w.dbp().set_bit());
@@ -470,12 +468,12 @@ pub trait RccBus: crate::Sealed {
470468

471469
/// Enable/disable peripheral
472470
pub trait Enable: RccBus {
473-
fn enable(rcc: &rcc::RegisterBlock);
474-
fn disable(rcc: &rcc::RegisterBlock);
471+
fn enable();
472+
fn disable();
475473
}
476474
/// Reset peripheral
477475
pub trait Reset: RccBus {
478-
fn reset(rcc: &rcc::RegisterBlock);
476+
fn reset();
479477
}
480478

481479
#[derive(Clone, Copy, Debug, PartialEq)]

‎src/rcc/enable.rs

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -11,21 +11,24 @@ macro_rules! bus {
1111
}
1212
impl Enable for crate::pac::$PER {
1313
#[inline(always)]
14-
fn enable(rcc: &rcc::RegisterBlock) {
14+
fn enable() {
15+
let rcc = unsafe { &(*RCC::ptr()) };
1516
unsafe {
1617
bb::set(Self::Bus::enr(rcc), $bit);
1718
}
1819
}
1920
#[inline(always)]
20-
fn disable(rcc: &rcc::RegisterBlock) {
21+
fn disable() {
22+
let rcc = unsafe { &(*RCC::ptr()) };
2123
unsafe {
2224
bb::clear(Self::Bus::enr(rcc), $bit);
2325
}
2426
}
2527
}
2628
impl Reset for crate::pac::$PER {
2729
#[inline(always)]
28-
fn reset(rcc: &rcc::RegisterBlock) {
30+
fn reset() {
31+
let rcc = unsafe { &(*RCC::ptr()) };
2932
unsafe {
3033
bb::set(Self::Bus::rstr(rcc), $bit);
3134
bb::clear(Self::Bus::rstr(rcc), $bit);
@@ -46,13 +49,15 @@ macro_rules! ahb_bus {
4649
}
4750
impl Enable for crate::pac::$PER {
4851
#[inline(always)]
49-
fn enable(rcc: &rcc::RegisterBlock) {
52+
fn enable() {
53+
let rcc = unsafe { &(*RCC::ptr()) };
5054
unsafe {
5155
bb::set(Self::Bus::enr(rcc), $bit);
5256
}
5357
}
5458
#[inline(always)]
55-
fn disable(rcc: &rcc::RegisterBlock) {
59+
fn disable() {
60+
let rcc = unsafe { &(*RCC::ptr()) };
5661
unsafe {
5762
bb::clear(Self::Bus::enr(rcc), $bit);
5863
}

‎src/serial.rs

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ use embedded_dma::{ReadBuffer, WriteBuffer};
7070
use crate::afio::MAPR;
7171
use crate::dma::{dma1, CircBuffer, RxDma, Transfer, TxDma, R, W};
7272
use crate::gpio::{self, Alternate, Input};
73-
use crate::pac::{RCC, USART1, USART2, USART3};
73+
use crate::pac::{USART1, USART2, USART3};
7474
use crate::rcc::{BusClock, Clocks, Enable, Reset};
7575
use crate::time::{Bps, U32Ext};
7676

@@ -292,9 +292,8 @@ impl<USART: Instance, PINS> Serial<USART, PINS> {
292292
PINS: Pins<USART>,
293293
{
294294
// Enable and reset USART
295-
let rcc = unsafe { &(*RCC::ptr()) };
296-
USART::enable(rcc);
297-
USART::reset(rcc);
295+
USART::enable();
296+
USART::reset();
298297

299298
PINS::remap(mapr);
300299

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