rcc_config_usb test

Author: burrbull

.github/workflows/ci.yml

@@ -35,3 +35,7 @@ jobs:
         with:
           command: check
           args: --features=${{ matrix.mcu }},rt --examples
+      - uses: actions-rs/cargo@v1
+        with:
+          command: test
+          args: --features=${{ matrix.mcu }} --target x86_64-unknown-linux-gnu --lib

src/rcc.rs

@@ -105,6 +105,7 @@ const HSI: u32 = 8_000_000; // Hz
 ///
 /// **NOTE**: Currently, it is not guaranteed that the exact frequencies selected will be
 /// used, only frequencies close to it.
+#[derive(Debug, Default, PartialEq)]
 pub struct CFGR {
     hse: Option<u32>,
     hclk: Option<u32>,
@@ -335,7 +336,7 @@ impl BKP {
 ///
 /// let clocks = rcc.cfgr.freeze(&mut flash.acr);
 /// ```
-#[derive(Clone, Copy)]
+#[derive(Clone, Copy, Debug, PartialEq)]
 pub struct Clocks {
     hclk: Hertz,
     pclk1: Hertz,
@@ -702,3 +703,39 @@ impl Config {
         }
     }
 }
+
+#[test]
+fn rcc_config_usb() {
+    use crate::time::U32Ext;
+    let cfgr = CFGR::default()
+        .use_hse(8.mhz())
+        .sysclk(48.mhz())
+        .pclk1(24.mhz());
+
+    let config = Config::from_cfgr(cfgr);
+    let config_expected = Config {
+        hse: Some(8_000_000),
+        pllmul: Some(4),
+        hpre: HPre::DIV1,
+        ppre1: PPre::DIV2,
+        ppre2: PPre::DIV1,
+        #[cfg(any(feature = "stm32f103", feature = "connectivity"))]
+        usbpre: UsbPre::DIV1,
+        adcpre: AdcPre::DIV8,
+    };
+    assert_eq!(config, config_expected);
+
+    let clocks = config.get_clocks();
+    let clocks_expected = Clocks {
+        hclk: 48.mhz().into(),
+        pclk1: 24.mhz().into(),
+        pclk2: 48.mhz().into(),
+        ppre1: 2,
+        ppre2: 1,
+        sysclk: 48.mhz().into(),
+        adcclk: 6.mhz().into(),
+        #[cfg(any(feature = "stm32f103", feature = "connectivity"))]
+        usbclk_valid: true,
+    };
+    assert_eq!(clocks, clocks_expected);
+}