Skip to content

Commit 48eb5fe

Browse files
committed
Fix Timer::syst
1 parent 8a69f77 commit 48eb5fe

File tree

2 files changed

+2
-2
lines changed

2 files changed

+2
-2
lines changed

CHANGELOG.md

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
1414
### Fixed
1515

1616
- Fix wrong frequency reported by `MonoTimer`
17+
- Fix wrong timings generated by `Timer::syst`
1718
- Fix period retrieval for timers
1819

1920
### Changed
@@ -23,7 +24,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
2324
- Improve `SPI` documentation
2425
- Improve `RCC` and `AFIO` register documentation
2526

26-
2727
## [v0.6.0] - 2020-06-06
2828

2929
### Breaking changes

src/timer.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -163,7 +163,7 @@ impl Timer<SYST> {
163163
syst.set_clock_source(SystClkSource::Core);
164164
Self {
165165
tim: syst,
166-
clk: clocks.sysclk(),
166+
clk: clocks.hclk(),
167167
}
168168
}
169169

0 commit comments

Comments
 (0)