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clear_idle_interrupt
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+28
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src/serial.rs

Lines changed: 28 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -294,21 +294,29 @@ where
294294
}
295295
}
296296

297-
/// Return true if the line idle status is set
297+
/// Returns true if the line idle status is set
298298
pub fn is_idle(&self) -> bool {
299299
self.usart.sr.read().idle().bit_is_set()
300300
}
301301

302-
/// Return true if the tx register is empty (and can accept data)
302+
/// Returns true if the tx register is empty (and can accept data)
303303
pub fn is_tx_empty(&self) -> bool {
304304
self.usart.sr.read().txe().bit_is_set()
305305
}
306306

307-
/// Return true if the rx register is not empty (and can be read)
307+
/// Returns true if the rx register is not empty (and can be read)
308308
pub fn is_rx_not_empty(&self) -> bool {
309309
self.usart.sr.read().rxne().bit_is_set()
310310
}
311311

312+
/// Clear idle line interrupt flag
313+
pub fn clear_idle_interrupt(&self) {
314+
unsafe {
315+
let _ = (*USART::ptr()).sr.read();
316+
let _ = (*USART::ptr()).dr.read();
317+
}
318+
}
319+
312320
/// Returns ownership of the borrowed register handles
313321
pub fn release(self) -> (USART, PINS) {
314322
(self.usart, self.pins)
@@ -383,14 +391,17 @@ impl<USART> Tx<USART>
383391
where
384392
USART: Instance,
385393
{
394+
/// Start listening for transmit interrupt event
386395
pub fn listen(&mut self) {
387396
unsafe { (*USART::ptr()).cr1.modify(|_, w| w.txeie().set_bit()) };
388397
}
389398

399+
/// Stop listening for transmit interrupt event
390400
pub fn unlisten(&mut self) {
391401
unsafe { (*USART::ptr()).cr1.modify(|_, w| w.txeie().clear_bit()) };
392402
}
393403

404+
/// Returns true if the tx register is empty (and can accept data)
394405
pub fn is_tx_empty(&self) -> bool {
395406
unsafe { (*USART::ptr()).sr.read().txe().bit_is_set() }
396407
}
@@ -400,29 +411,43 @@ impl<USART> Rx<USART>
400411
where
401412
USART: Instance,
402413
{
414+
/// Start listening for receive interrupt event
403415
pub fn listen(&mut self) {
404416
unsafe { (*USART::ptr()).cr1.modify(|_, w| w.rxneie().set_bit()) };
405417
}
406418

419+
/// Stop listening for receive interrupt event
407420
pub fn unlisten(&mut self) {
408421
unsafe { (*USART::ptr()).cr1.modify(|_, w| w.rxneie().clear_bit()) };
409422
}
410423

424+
/// Start listening for idle interrupt event
411425
pub fn listen_idle(&mut self) {
412426
unsafe { (*USART::ptr()).cr1.modify(|_, w| w.idleie().set_bit()) };
413427
}
414428

429+
/// Stop listening for idle interrupt event
415430
pub fn unlisten_idle(&mut self) {
416431
unsafe { (*USART::ptr()).cr1.modify(|_, w| w.idleie().clear_bit()) };
417432
}
418433

434+
/// Returns true if the line idle status is set
419435
pub fn is_idle(&self) -> bool {
420436
unsafe { (*USART::ptr()).sr.read().idle().bit_is_set() }
421437
}
422438

439+
/// Returns true if the rx register is not empty (and can be read)
423440
pub fn is_rx_not_empty(&self) -> bool {
424441
unsafe { (*USART::ptr()).sr.read().rxne().bit_is_set() }
425442
}
443+
444+
/// Clear idle line interrupt flag
445+
pub fn clear_idle_interrupt(&self) {
446+
unsafe {
447+
let _ = (*USART::ptr()).sr.read();
448+
let _ = (*USART::ptr()).dr.read();
449+
}
450+
}
426451
}
427452

428453
impl<USART> crate::hal::serial::Read<u8> for Rx<USART>

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