From e3dfa532b5bd5940aca3c70811072c58d7cbd3a2 Mon Sep 17 00:00:00 2001 From: Janek Date: Thu, 7 Dec 2023 11:11:59 +0100 Subject: [PATCH 1/3] Add Pin PB6 as TIM16 PWM output --- src/timers.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/src/timers.rs b/src/timers.rs index f7aa80c..136bc93 100644 --- a/src/timers.rs +++ b/src/timers.rs @@ -327,6 +327,7 @@ channel_impl!( TIM16, PinC1, PA6, Alternate; TIM16, PinC1, PB8, Alternate; + TIM16, PinC1N, PB6, Alternate; TIM17, PinC1, PA7, Alternate; TIM17, PinC1, PB9, Alternate; From 0abb3c3004767c179504d52f10b6aa95befa263d Mon Sep 17 00:00:00 2001 From: Janek Date: Thu, 7 Dec 2023 11:16:16 +0100 Subject: [PATCH 2/3] Implement PWM output on complementary Channels This was not previously implemented for single channel PWMs with complementary outputs --- src/pwm.rs | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/src/pwm.rs b/src/pwm.rs index d83067f..27fff02 100644 --- a/src/pwm.rs +++ b/src/pwm.rs @@ -75,6 +75,9 @@ pins_impl!( (P2), (PinC2), (C2); (P3), (PinC3), (C3); (P4), (PinC4), (C4); + (P1N), (PinC1N), (C1N); + (P2N), (PinC2N), (C2N); + (P3N), (PinC3N), (C3N); ); impl, P2: PinC1> PinC1 for (P1, P2) {} @@ -803,7 +806,7 @@ macro_rules! pwm_1_channel_with_complementary_outputs { rcc.regs.$apbrstr.modify(|_, w| w.$timXrst().set_bit()); rcc.regs.$apbrstr.modify(|_, w| w.$timXrst().clear_bit()); - if PINS::C1 { + if PINS::C1 || PINS::C1N { tim.ccmr1_output().modify(|_, w| w.oc1pe().set_bit().oc1m().bits(6)); } @@ -868,6 +871,35 @@ macro_rules! pwm_1_channel_with_complementary_outputs { unsafe { (*$TIMX::ptr()).ccr1.write(|w| w.ccr().bits(duty.into())) } } } + + impl hal::PwmPin for PwmChannels<$TIMX, C1N> { + type Duty = u16; + + //NOTE(unsafe) atomic write with no side effects + fn disable(&mut self) { + unsafe { (*($TIMX::ptr())).ccer.modify(|_, w| w.cc1ne().clear_bit()) }; + } + + //NOTE(unsafe) atomic write with no side effects + fn enable(&mut self) { + unsafe { (*($TIMX::ptr())).ccer.modify(|_, w| w.cc1ne().set_bit()) }; + } + + //NOTE(unsafe) atomic read with no side effects + fn get_duty(&self) -> u16 { + unsafe { (*$TIMX::ptr()).ccr1.read().ccr().bits() as u16 } + } + + //NOTE(unsafe) atomic read with no side effects + fn get_max_duty(&self) -> u16 { + unsafe { (*$TIMX::ptr()).arr.read().arr().bits() as u16 } + } + + //NOTE(unsafe) atomic write with no side effects + fn set_duty(&mut self, duty: u16) { + unsafe { (*$TIMX::ptr()).ccr1.write(|w| w.ccr().bits(duty.into())) } + } + } )+ }; } From 76fa66f7c618f164cb4c507481bacbd78847a85c Mon Sep 17 00:00:00 2001 From: Janek Date: Thu, 7 Dec 2023 11:18:14 +0100 Subject: [PATCH 3/3] Update CHANGELOG.md --- CHANGELOG.md | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 525825e..9376b72 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Added - PWM complementary output capability for TIM1 with new example to demonstrate +- PWM output on complementary channels only for single channel timers (TIM16 + TIM17) ### Changed