diff --git a/CHANGELOG.md b/CHANGELOG.md
index e95ebc7..f2c1fdb 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -16,6 +16,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Provide getters to serial status flags idle/txe/rxne/tc.
 - Provide ability to reset timer UIF interrupt flag
 - PWM complementary output capability for TIM1 with new example to demonstrate
+- PWM output on complementary channels only for single channel timers (TIM16 + TIM17)
 
 ### Fixed
 
diff --git a/src/pwm.rs b/src/pwm.rs
index d83067f..27fff02 100644
--- a/src/pwm.rs
+++ b/src/pwm.rs
@@ -75,6 +75,9 @@ pins_impl!(
     (P2), (PinC2), (C2);
     (P3), (PinC3), (C3);
     (P4), (PinC4), (C4);
+    (P1N), (PinC1N), (C1N);
+    (P2N), (PinC2N), (C2N);
+    (P3N), (PinC3N), (C3N);
 );
 
 impl<TIM, P1: PinC1<TIM>, P2: PinC1<TIM>> PinC1<TIM> for (P1, P2) {}
@@ -803,7 +806,7 @@ macro_rules! pwm_1_channel_with_complementary_outputs {
                 rcc.regs.$apbrstr.modify(|_, w| w.$timXrst().set_bit());
                 rcc.regs.$apbrstr.modify(|_, w| w.$timXrst().clear_bit());
 
-                if PINS::C1 {
+                if PINS::C1 || PINS::C1N {
                     tim.ccmr1_output().modify(|_, w| w.oc1pe().set_bit().oc1m().bits(6));
                 }
 
@@ -868,6 +871,35 @@ macro_rules! pwm_1_channel_with_complementary_outputs {
                     unsafe { (*$TIMX::ptr()).ccr1.write(|w| w.ccr().bits(duty.into())) }
                 }
             }
+
+            impl hal::PwmPin for PwmChannels<$TIMX, C1N> {
+                type Duty = u16;
+
+                //NOTE(unsafe) atomic write with no side effects
+                fn disable(&mut self) {
+                    unsafe { (*($TIMX::ptr())).ccer.modify(|_, w| w.cc1ne().clear_bit()) };
+                }
+
+                //NOTE(unsafe) atomic write with no side effects
+                fn enable(&mut self) {
+                    unsafe { (*($TIMX::ptr())).ccer.modify(|_, w| w.cc1ne().set_bit()) };
+                }
+
+                //NOTE(unsafe) atomic read with no side effects
+                fn get_duty(&self) -> u16 {
+                    unsafe { (*$TIMX::ptr()).ccr1.read().ccr().bits() as u16 }
+                }
+
+                //NOTE(unsafe) atomic read with no side effects
+                fn get_max_duty(&self) -> u16 {
+                    unsafe { (*$TIMX::ptr()).arr.read().arr().bits() as u16 }
+                }
+
+                //NOTE(unsafe) atomic write with no side effects
+                fn set_duty(&mut self, duty: u16) {
+                    unsafe { (*$TIMX::ptr()).ccr1.write(|w| w.ccr().bits(duty.into())) }
+                }
+            }
         )+
     };
 }
diff --git a/src/timers.rs b/src/timers.rs
index f7aa80c..136bc93 100644
--- a/src/timers.rs
+++ b/src/timers.rs
@@ -327,6 +327,7 @@ channel_impl!(
 
     TIM16, PinC1, PA6, Alternate<AF5>;
     TIM16, PinC1, PB8, Alternate<AF2>;
+    TIM16, PinC1N, PB6, Alternate<AF2>;
 
     TIM17, PinC1, PA7, Alternate<AF5>;
     TIM17, PinC1, PB9, Alternate<AF2>;