From d940d8bbb4b4fc8a23fc31c6dff7805ae2af1e1f Mon Sep 17 00:00:00 2001 From: mitchmindtree Date: Mon, 20 Jul 2020 00:17:17 +0200 Subject: [PATCH 1/2] Rewrite `stm32f4` setup with svd generated registers @thalesfragoso this is the patch I mentioned on matrix. Curiously, @therealprof didn't need it, and you mentioned the current setup has worked for you in the past as well. Just to clarify, the board I'm testing is STM32F407G-DISC1 - but I imagine behaviour should be the same across F407s? As you mentioned it would need either a critical section or access to the `&RCC` and `&SYSCFG` passed as arguments to the function directly. I think I'd opt for the latter approach, and not call this from inside `Eth::new`, but rather have a separate `configure_rcc` (or something like this) that the user can call separately before `Eth::new` is called. If it's a separate function, the user can do ```rust configure_rcc(&p.RCC, &p.SYSCFG); ``` before they set the RCC clock speeds and call `freeze`. If we really wanted to make sure this was called prior to `Eth::new`, we could do so by returning some type from `configure_rcc` that must be passed as an argument to `Eth::new`. I'll double check the behaviour of `master` compared to this patch again tomorrow once I'm back at work on this. I thought I'd open this in the meantime in case you were curious! --- src/setup.rs | 33 +++++++++++++-------------------- 1 file changed, 13 insertions(+), 20 deletions(-) diff --git a/src/setup.rs b/src/setup.rs index 1ec1ec3..23cd07f 100644 --- a/src/setup.rs +++ b/src/setup.rs @@ -1,6 +1,5 @@ #[cfg(feature = "stm32f4xx-hal")] use stm32f4xx_hal::{ - bb, gpio::{ gpioa::{PA1, PA2, PA7}, gpiob::{PB11, PB12, PB13}, @@ -31,35 +30,29 @@ use stm32f7xx_hal::{ pub(crate) fn setup() { #[cfg(feature = "stm32f4xx-hal")] unsafe { - const SYSCFG_BIT: u8 = 14; - const ETH_MAC_BIT: u8 = 25; - const ETH_TX_BIT: u8 = 26; - const ETH_RX_BIT: u8 = 27; - const MII_RMII_BIT: u8 = 23; - //NOTE(unsafe) This will only be used for atomic writes with no side-effects let rcc = &*RCC::ptr(); let syscfg = &*SYSCFG::ptr(); - // Enable syscfg clock - bb::set(&rcc.apb2enr, SYSCFG_BIT); + // Enable syscfg clock. + rcc.apb2enr.write(|w| w.syscfgen().set_bit()); if rcc.ahb1enr.read().ethmacen().bit_is_set() { // pmc must be changed with the ethernet controller disabled or under reset - bb::clear(&rcc.ahb1enr, ETH_MAC_BIT); + rcc.ahb1enr.write(|w| w.ethmacen().clear_bit()); } - // select MII or RMII mode - // 0 = MII, 1 = RMII - bb::set(&syscfg.pmc, MII_RMII_BIT); - // enable ethernet clocks - bb::set(&rcc.ahb1enr, ETH_MAC_BIT); - bb::set(&rcc.ahb1enr, ETH_TX_BIT); - bb::set(&rcc.ahb1enr, ETH_RX_BIT); + // 0 = MII, 1 = RMII. + syscfg.pmc.write(|w| w.mii_rmii_sel().set_bit()); + + // Enable ethernet clocks. + rcc.ahb1enr.write(|w| w.ethmacen().set_bit()); + rcc.ahb1enr.write(|w| w.ethmactxen().set_bit()); + rcc.ahb1enr.write(|w| w.ethmacrxen().set_bit()); - // reset pulse - bb::set(&rcc.ahb1rstr, ETH_MAC_BIT); - bb::clear(&rcc.ahb1rstr, ETH_MAC_BIT); + // Reset pulse. + rcc.ahb1rstr.write(|w| w.ethmacrst().set_bit()); + rcc.ahb1rstr.write(|w| w.ethmacrst().clear_bit()); } #[cfg(feature = "stm32f7xx-hal")] //stm32f7xx-hal does not currently have bitbanding From a116fdef2f56296ab5e86991fd24ca606911dad8 Mon Sep 17 00:00:00 2001 From: mitchmindtree Date: Tue, 28 Jul 2020 12:30:27 +0200 Subject: [PATCH 2/2] Use modify rather than write in stm32f407 setup --- src/setup.rs | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/setup.rs b/src/setup.rs index 23cd07f..74d79fe 100644 --- a/src/setup.rs +++ b/src/setup.rs @@ -35,24 +35,24 @@ pub(crate) fn setup() { let syscfg = &*SYSCFG::ptr(); // Enable syscfg clock. - rcc.apb2enr.write(|w| w.syscfgen().set_bit()); + rcc.apb2enr.modify(|_, w| w.syscfgen().set_bit()); if rcc.ahb1enr.read().ethmacen().bit_is_set() { // pmc must be changed with the ethernet controller disabled or under reset - rcc.ahb1enr.write(|w| w.ethmacen().clear_bit()); + rcc.ahb1enr.modify(|_, w| w.ethmacen().clear_bit()); } // 0 = MII, 1 = RMII. - syscfg.pmc.write(|w| w.mii_rmii_sel().set_bit()); + syscfg.pmc.modify(|_, w| w.mii_rmii_sel().set_bit()); // Enable ethernet clocks. - rcc.ahb1enr.write(|w| w.ethmacen().set_bit()); - rcc.ahb1enr.write(|w| w.ethmactxen().set_bit()); - rcc.ahb1enr.write(|w| w.ethmacrxen().set_bit()); + rcc.ahb1enr.modify(|_, w| w.ethmacen().set_bit()); + rcc.ahb1enr.modify(|_, w| w.ethmactxen().set_bit()); + rcc.ahb1enr.modify(|_, w| w.ethmacrxen().set_bit()); // Reset pulse. - rcc.ahb1rstr.write(|w| w.ethmacrst().set_bit()); - rcc.ahb1rstr.write(|w| w.ethmacrst().clear_bit()); + rcc.ahb1rstr.modify(|_, w| w.ethmacrst().set_bit()); + rcc.ahb1rstr.modify(|_, w| w.ethmacrst().clear_bit()); } #[cfg(feature = "stm32f7xx-hal")] //stm32f7xx-hal does not currently have bitbanding