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Merge pull request #80 from stm32-rs/fix_79
Fix a logic error
2 parents 7c22c31 + ba6d227 commit f811713

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2 files changed

+4
-2
lines changed

2 files changed

+4
-2
lines changed

src/dma/tx/descriptor.rs

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -135,7 +135,9 @@ impl TxDescriptor {
135135
fn set_buffer1_len(&mut self, len: usize) {
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unsafe {
137137
self.desc.modify(1, |w| {
138-
(w & !TXDESC_1_TBS_MASK) | ((len as u32) << TXDESC_1_TBS_SHIFT)
138+
let masked_len = w & !TXDESC_1_TBS_MASK;
139+
let with_len = masked_len | ((len as u32) << TXDESC_1_TBS_SHIFT);
140+
with_len
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});
140142
}
141143
}

src/dma/tx/mod.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -80,7 +80,7 @@ impl<'ring> TxRing<'ring> {
8080

8181
/// If this returns `true`, the next `send` will succeed.
8282
pub fn next_entry_available(&self) -> bool {
83-
!self.entries[self.next_entry].is_available()
83+
self.entries[self.next_entry].is_available()
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}
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8686
/// Check if we can send the next TX entry.

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