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datdenkiknietdatdenkikniet
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Make f series compile again
1 parent a2e3061 commit f646ab0

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9 files changed

+77
-83
lines changed

9 files changed

+77
-83
lines changed

‎src/dma/mod.rs

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -6,12 +6,6 @@ use cortex_m::peripheral::NVIC;
66

77
use crate::{peripherals::ETHERNET_DMA, stm32::Interrupt};
88

9-
#[cfg(feature = "f-series")]
10-
type ETHERNET_MTL = ();
11-
12-
#[cfg(feature = "stm32h7xx-hal")]
13-
use crate::stm32::ETHERNET_MTL;
14-
159
#[cfg(feature = "smoltcp-phy")]
1610
mod smoltcp_phy;
1711
#[cfg(feature = "smoltcp-phy")]
@@ -77,7 +71,7 @@ pub struct EthernetDMA<'rx, 'tx> {
7771
pub(crate) struct DmaParts {
7872
pub eth_dma: ETHERNET_DMA,
7973
#[cfg(feature = "stm32h7xx-hal")]
80-
pub eth_mtl: ETHERNET_MTL,
74+
pub eth_mtl: crate::stm32::ETHERNET_MTL,
8175
}
8276

8377
impl<'rx, 'tx> EthernetDMA<'rx, 'tx> {

‎src/dma/rx/f_series_desc.rs

Lines changed: 14 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -59,8 +59,7 @@ impl RxDescriptor {
5959
}
6060

6161
pub(super) fn setup(&mut self, buffer: &mut [u8]) {
62-
self.set_buffer(buffer);
63-
self.set_owned();
62+
self.set_owned(buffer);
6463
}
6564

6665
/// Is owned by the DMA engine?
@@ -71,7 +70,9 @@ impl RxDescriptor {
7170
/// Pass ownership to the DMA engine
7271
///
7372
/// Overrides old timestamp data
74-
pub(super) fn set_owned(&mut self) {
73+
pub(super) fn set_owned(&mut self, buffer: &mut [u8]) {
74+
self.set_buffer(buffer);
75+
7576
// "Preceding reads and writes cannot be moved past subsequent writes."
7677
#[cfg(feature = "fence")]
7778
atomic::fence(Ordering::Release);
@@ -125,11 +126,15 @@ impl RxDescriptor {
125126
((self.inner_raw.read(0) >> RXDESC_0_FL_SHIFT) & RXDESC_0_FL_MASK) as usize
126127
}
127128

128-
pub(super) fn take_received(&mut self, packet_id: Option<PacketId>) -> Result<(), RxError> {
129+
pub(super) fn take_received(
130+
&mut self,
131+
packet_id: Option<PacketId>,
132+
buffer: &mut [u8],
133+
) -> Result<(), RxError> {
129134
if self.is_owned() {
130135
Err(RxError::WouldBlock)
131136
} else if self.has_error() {
132-
self.set_owned();
137+
self.set_owned(buffer);
133138
Err(RxError::DmaError)
134139
} else if self.is_first() && self.is_last() {
135140
// "Subsequent reads and writes cannot be moved ahead of preceding reads."
@@ -143,22 +148,22 @@ impl RxDescriptor {
143148

144149
Ok(())
145150
} else {
146-
self.set_owned();
151+
self.set_owned(buffer);
147152
Err(RxError::Truncated)
148153
}
149154
}
150155

151156
pub(super) fn set_end_of_ring(&mut self) {
152157
unsafe { self.inner_raw.modify(1, |w| w | RXDESC_1_RER) }
153158
}
159+
}
154160

161+
#[cfg(feature = "ptp")]
162+
impl RxDescriptor {
155163
pub(super) fn packet_id(&self) -> Option<&PacketId> {
156164
self.packet_id.as_ref()
157165
}
158-
}
159166

160-
#[cfg(feature = "ptp")]
161-
impl RxDescriptor {
162167
/// Get PTP timestamps if available
163168
pub(super) fn read_timestamp(&self) -> Option<Timestamp> {
164169
#[cfg(not(feature = "stm32f1xx-hal"))]

‎src/dma/rx/h_desc.rs

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -136,11 +136,12 @@ impl RxDescriptor {
136136
}
137137

138138
pub(super) fn setup(&mut self, buffer: &[u8]) {
139-
self.set_owned(buffer.as_ptr());
139+
self.set_owned(buffer);
140140
}
141141

142142
/// Pass ownership to the DMA engine
143-
pub(super) fn set_owned(&mut self, buffer: *const u8) {
143+
pub(super) fn set_owned(&mut self, buffer: &[u8]) {
144+
let buffer = buffer.as_ptr();
144145
self.set_buffer(buffer);
145146

146147
// "Preceding reads and writes cannot be moved past subsequent writes."
@@ -205,7 +206,7 @@ impl RxDescriptor {
205206

206207
Ok(())
207208
} else {
208-
self.set_owned(buffer.as_ptr());
209+
self.set_owned(buffer);
209210
Err(RxError::Truncated)
210211
}
211212
}

‎src/dma/rx/mod.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -280,7 +280,7 @@ impl<'a> core::ops::DerefMut for RxPacket<'a> {
280280

281281
impl<'a> Drop for RxPacket<'a> {
282282
fn drop(&mut self) {
283-
self.entry.set_owned(self.buffer.as_ptr());
283+
self.entry.set_owned(self.buffer);
284284
}
285285
}
286286

‎src/dma/tx/f_series_desc.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -144,14 +144,14 @@ impl TxDescriptor {
144144
pub(super) fn set_end_of_ring(&mut self) {
145145
unsafe { self.inner_raw.modify(0, |w| w | TXDESC_0_TER) };
146146
}
147+
}
147148

149+
#[cfg(feature = "ptp")]
150+
impl TxDescriptor {
148151
pub(super) fn packet_id(&self) -> Option<&PacketId> {
149152
self.packet_id.as_ref()
150153
}
151-
}
152154

153-
#[cfg(feature = "ptp")]
154-
impl TxDescriptor {
155155
fn read_timestamp(&mut self) -> Option<Timestamp> {
156156
let tdes0 = self.inner_raw.read(0);
157157

‎src/dma/tx/mod.rs

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@ pub(crate) struct TxRing<'data, STATE> {
4141
impl<'data, STATE> TxRing<'data, STATE> {
4242
pub fn running_state(&self, eth_dma: &ETHERNET_DMA) -> RunningState {
4343
#[cfg(feature = "f-series")]
44-
let tx_status = eth_dma.dmasr().read().tps().bits();
44+
let tx_status = eth_dma.dmasr.read().tps().bits();
4545

4646
#[cfg(feature = "stm32h7xx-hal")]
4747
let tx_status = eth_dma.dmadsr.read().tps0().bits();
@@ -97,7 +97,7 @@ impl<'data> TxRing<'data, NotRunning> {
9797

9898
#[cfg(feature = "f-series")]
9999
// Set end of ring register
100-
self.ring.last_descriptor().set_end_of_ring();
100+
self.ring.last_descriptor_mut().set_end_of_ring();
101101

102102
let ring_ptr = self.ring.descriptors_start_address();
103103

@@ -235,20 +235,20 @@ impl<'data> TxRing<'data, Running> {
235235
impl<'data> TxRing<'data, Running> {
236236
pub(crate) fn collect_timestamps(&mut self) {
237237
for descriptor in self.ring.descriptors_mut() {
238-
f_descriptor.attach_timestamp();
238+
descriptor.attach_timestamp();
239239
}
240240
}
241241

242242
pub(crate) fn get_timestamp_for_id(&self, id: PacketId) -> Result<Timestamp, TimestampError> {
243243
let descriptor = if let Some(descriptor) =
244244
self.ring.descriptors().find(|d| d.packet_id() == Some(&id))
245245
{
246-
f_descriptor
246+
descriptor
247247
} else {
248248
return Err(TimestampError::IdNotFound);
249249
};
250250

251-
f_descriptor
251+
descriptor
252252
.timestamp()
253253
.map(|t| *t)
254254
.ok_or(TimestampError::NotYetTimestamped)

‎src/lib.rs

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -111,7 +111,7 @@ where
111111
// Congfigure and start up the ethernet DMA.
112112
let dma = EthernetDMA::new(
113113
DmaParts {
114-
eth_dma: parts.dma,
114+
eth_dma: parts.dma.into(),
115115
#[cfg(feature = "stm32h7xx-hal")]
116116
eth_mtl: parts.mtl,
117117
},
@@ -195,15 +195,24 @@ where
195195
let eth_mac = parts.mac.into();
196196

197197
// Congfigure and start up the ethernet DMA.
198-
let dma = EthernetDMA::new(parts.dma.into(), rx_buffer, tx_buffer);
198+
let dma = EthernetDMA::new(
199+
DmaParts {
200+
eth_dma: parts.dma.into(),
201+
},
202+
rx_buffer,
203+
tx_buffer,
204+
);
199205

200206
// Configure the ethernet PTP
201207
#[cfg(feature = "ptp")]
202208
let ptp = EthernetPTP::new(parts.ptp.into(), clocks, &dma);
203209

204210
// Configure the ethernet MAC
205211
let mac = EthernetMAC::new(
206-
MacParts { eth_mac, eth_mmc },
212+
MacParts {
213+
eth_mac,
214+
eth_mmc: parts.mmc,
215+
},
207216
clocks,
208217
Speed::FullDuplexBase100Tx,
209218
&dma,

‎src/mac/miim.rs

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,8 @@
11
pub use ieee802_3_miim::Miim;
2-
32
pub use ieee802_3_miim::*;
43

4+
use core::ops::{Deref, DerefMut};
5+
56
use crate::{peripherals::ETHERNET_MAC, stm32::ethernet_mac::MACMIIAR};
67

78
use super::EthernetMAC;
@@ -157,7 +158,7 @@ where
157158
MDIO: MdioPin,
158159
MDC: MdcPin,
159160
{
160-
pub(crate) eth_mac: EthernetMAC,
161+
eth_mac: EthernetMAC,
161162
mdio: MDIO,
162163
mdc: MDC,
163164
}
@@ -226,7 +227,7 @@ where
226227
}
227228
}
228229

229-
impl<MDIO, MDC> miim::Miim for EthernetMACWithMii<MDIO, MDC>
230+
impl<MDIO, MDC> Miim for EthernetMACWithMii<MDIO, MDC>
230231
where
231232
MDIO: MdioPin,
232233
MDC: MdcPin,

‎src/mac/mod.rs

Lines changed: 33 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -10,15 +10,15 @@ pub use miim::*;
1010
pub(crate) struct MacParts {
1111
pub eth_mac: ETHERNET_MAC,
1212
#[cfg(feature = "f-series")]
13-
pub eth_mmc: ETHERNET_MMC,
13+
pub eth_mmc: crate::stm32::ETHERNET_MMC,
1414
}
1515

1616
impl MacParts {
1717
fn enable_promicious_mode(&self) {
1818
let Self { eth_mac, .. } = self;
1919

2020
#[cfg(feature = "f-series")]
21-
let (mac_filter_reg, flow_control) = (&eth_mac.macffr, &eth_mac.macfcr);
21+
let (mac_filter, flow_control) = (&eth_mac.macffr, &eth_mac.macfcr);
2222
#[cfg(feature = "stm32h7xx-hal")]
2323
let (mac_filter, flow_control) = (&eth_mac.macpfr, &eth_mac.macqtx_fcr);
2424

@@ -42,14 +42,9 @@ impl MacParts {
4242
}
4343

4444
fn disable_mmc_interrupts(&self) {
45-
let Self {
46-
eth_mac,
47-
#[cfg(feature = "f-series")]
48-
eth_mmc,
49-
} = self;
50-
5145
#[cfg(feature = "f-series")]
5246
{
47+
let eth_mmc = &self.eth_mmc;
5348
// Disable all MMC RX interrupts
5449
eth_mmc
5550
.mmcrimr
@@ -69,6 +64,8 @@ impl MacParts {
6964

7065
#[cfg(feature = "stm32h7xx-hal")]
7166
{
67+
let eth_mac = &self.eth_mac;
68+
7269
// Disable all MMC RX interrupts
7370
eth_mac.mmc_rx_interrupt_mask.write(|w| {
7471
w.rxlpitrcim()
@@ -163,11 +160,7 @@ impl EthernetMAC {
163160
// it doesn't work.
164161
_dma: &EthernetDMA,
165162
) -> Result<Self, WrongClock> {
166-
let MacParts {
167-
eth_mac,
168-
#[cfg(feature = "f-series")]
169-
eth_mmc,
170-
} = &parts;
163+
let eth_mac = &parts.eth_mac;
171164

172165
// TODO: configure MDIOS
173166
#[cfg(feature = "f-series")]
@@ -218,12 +211,7 @@ impl EthernetMAC {
218211
.dr()
219212
.set_bit();
220213

221-
// Fast Ethernet speed
222-
w.fes()
223-
.set_bit()
224-
// Duplex mode
225-
.dm()
226-
.set_bit()
214+
w
227215
// Receiver enable
228216
.re()
229217
.set_bit()
@@ -244,6 +232,31 @@ impl EthernetMAC {
244232
Ok(me)
245233
}
246234

235+
/// Set the Ethernet Speed at which the MAC communicates
236+
///
237+
/// Note that this does _not_ affect the PHY in any way. To
238+
/// configure the PHY, use [`EthernetMACWithMii`] (see: [`Self::with_mii`])
239+
/// or [`Stm32Mii`] (see: [`Self::mii`])
240+
pub fn set_speed(&mut self, speed: Speed) {
241+
self.eth_mac.maccr.modify(|_, w| match speed {
242+
Speed::HalfDuplexBase10T => w.fes().clear_bit().dm().clear_bit(),
243+
Speed::FullDuplexBase10T => w.fes().clear_bit().dm().set_bit(),
244+
Speed::HalfDuplexBase100Tx => w.fes().set_bit().dm().clear_bit(),
245+
Speed::FullDuplexBase100Tx => w.fes().set_bit().dm().set_bit(),
246+
});
247+
}
248+
249+
/// Get the Ethernet Speed at which the MAC communicates
250+
pub fn get_speed(&self) -> Speed {
251+
let cr = self.eth_mac.maccr.read();
252+
match (cr.fes().bit_is_set(), cr.dm().bit_is_set()) {
253+
(false, false) => Speed::HalfDuplexBase10T,
254+
(false, true) => Speed::FullDuplexBase10T,
255+
(true, false) => Speed::HalfDuplexBase100Tx,
256+
(true, true) => Speed::FullDuplexBase100Tx,
257+
}
258+
}
259+
247260
/// Borrow access to the MAC's SMI.
248261
///
249262
/// Allows for controlling and monitoring any PHYs that may be accessible via the MDIO/MDC
@@ -271,36 +284,7 @@ impl EthernetMAC {
271284
MDIO: MdioPin,
272285
MDC: MdcPin,
273286
{
274-
EthernetMACWithMii {
275-
eth_mac: self,
276-
mdio,
277-
mdc,
278-
}
279-
}
280-
281-
/// Set the Ethernet Speed at which the MAC communicates
282-
///
283-
/// Note that this does _not_ affect the PHY in any way. To
284-
/// configure the PHY, use [`EthernetMACWithMii`] (see: [`Self::with_mii`])
285-
/// or [`Stm32Mii`] (see: [`Self::mii`])
286-
pub fn set_speed(&mut self, speed: Speed) {
287-
self.eth_mac.maccr.modify(|_, w| match speed {
288-
Speed::HalfDuplexBase10T => w.fes().clear_bit().dm().clear_bit(),
289-
Speed::FullDuplexBase10T => w.fes().clear_bit().dm().set_bit(),
290-
Speed::HalfDuplexBase100Tx => w.fes().set_bit().dm().clear_bit(),
291-
Speed::FullDuplexBase100Tx => w.fes().set_bit().dm().set_bit(),
292-
});
293-
}
294-
295-
/// Get the Ethernet Speed at which the MAC communicates
296-
pub fn get_speed(&self) -> Speed {
297-
let cr = self.eth_mac.maccr.read();
298-
match (cr.fes().bit_is_set(), cr.dm().bit_is_set()) {
299-
(false, false) => Speed::HalfDuplexBase10T,
300-
(false, true) => Speed::FullDuplexBase10T,
301-
(true, false) => Speed::HalfDuplexBase100Tx,
302-
(true, true) => Speed::FullDuplexBase100Tx,
303-
}
287+
EthernetMACWithMii::new(self, mdio, mdc)
304288
}
305289

306290
#[cfg(feature = "ptp")]

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