MAC module

Author: datdenkikniet

src/lib.rs

@@ -55,7 +55,7 @@ pub use smoltcp;
 #[cfg(feature = "device-selected")]
 use {
     dma::{EthernetDMA, RxRingEntry, TxRingEntry},
-    mac::{EthernetMAC, EthernetMACWithMii, MdcPin, MdioPin, Speed, WrongClock},
+    mac::{EthernetMAC, EthernetMACWithMii, MacParts, MdcPin, MdioPin, Speed, WrongClock},
     setup::*,
 };
 
@@ -140,8 +140,6 @@ where
     // Set up the clocks and reset the MAC periperhal
     setup::setup();
 
-    let eth_mac = parts.mac.into();
-
     // Congfigure and start up the ethernet DMA.
     let dma = EthernetDMA::new(parts.dma.into(), rx_buffer, tx_buffer);
 
@@ -154,8 +152,14 @@ where
         &dma,
     );
 
+    let mac_parts = MacParts {
+        eth_mac: parts.mac.into(),
+        #[cfg(feature = "f-series")]
+        eth_mmc: parts.mmc.into(),
+    };
+
     // Configure the ethernet MAC
-    let mac = EthernetMAC::new(eth_mac, parts.mmc, clocks, Speed::FullDuplexBase100Tx, &dma)?;
+    let mac = EthernetMAC::new(mac_parts, clocks, Speed::FullDuplexBase100Tx, &dma)?;
 
     let parts = Parts {
         mac,
@@ -214,8 +218,6 @@ where
     // Set up the clocks and reset the MAC periperhal
     setup::setup();
 
-    let eth_mac = parts.mac.into();
-
     // Congfigure and start up the ethernet DMA.
     let dma = EthernetDMA::new(parts.dma.into(), rx_buffer, tx_buffer);
 
@@ -228,9 +230,15 @@ where
         &dma,
     );
 
+    let mac_parts = MacParts {
+        eth_mac: parts.mac.into(),
+        #[cfg(feature = "f-series")]
+        eth_mmc: parts.mmc.into(),
+    };
+
     // Configure the ethernet MAC
-    let mac = EthernetMAC::new(eth_mac, parts.mmc, clocks, Speed::FullDuplexBase100Tx, &dma)?
-        .with_mii(mdio, mdc);
+    let mac =
+        EthernetMAC::new(mac_parts, clocks, Speed::FullDuplexBase100Tx, &dma)?.with_mii(mdio, mdc);
 
     let parts = Parts {
         mac,

src/mac/miim.rs

@@ -0,0 +1,76 @@
+use crate::peripherals::ETHERNET_MAC;
+use crate::stm32::ethernet_mac::MACMIIAR;
+
+#[inline(always)]
+fn miim_wait_ready(iar: &MACMIIAR) {
+    while iar.read().mb().bit_is_set() {}
+}
+
+#[inline(always)]
+pub(crate) fn miim_write(eth_mac: &mut ETHERNET_MAC, phy: u8, reg: u8, data: u16) {
+    miim_wait_ready(&eth_mac.macmiiar);
+    eth_mac.macmiidr.write(|w| w.md().bits(data));
+
+    miim_wait_ready(&eth_mac.macmiiar);
+
+    eth_mac.macmiiar.modify(|_, w| {
+        w.pa()
+            .bits(phy)
+            .mr()
+            .bits(reg)
+            /* Write operation MW=1*/
+            .mw()
+            .set_bit()
+            .mb()
+            .set_bit()
+    });
+    miim_wait_ready(&eth_mac.macmiiar);
+}
+
+#[inline(always)]
+pub(crate) fn miim_read(eth_mac: &mut ETHERNET_MAC, phy: u8, reg: u8) -> u16 {
+    miim_wait_ready(&eth_mac.macmiiar);
+    eth_mac.macmiiar.modify(|_, w| {
+        w.pa()
+            .bits(phy)
+            .mr()
+            .bits(reg)
+            /* Read operation MW=0 */
+            .mw()
+            .clear_bit()
+            .mb()
+            .set_bit()
+    });
+    miim_wait_ready(&eth_mac.macmiiar);
+
+    // Return value:
+    eth_mac.macmiidr.read().md().bits()
+}
+
+#[cfg(feature = "stm32f4xx-hal")]
+mod pin_impls {
+    use crate::hal::gpio::{gpioa::PA2, gpioc::PC1, Alternate};
+
+    const AF11: u8 = 11;
+
+    unsafe impl crate::mac::MdioPin for PA2<Alternate<AF11>> {}
+    unsafe impl crate::mac::MdcPin for PC1<Alternate<AF11>> {}
+}
+
+#[cfg(feature = "stm32f7xx-hal")]
+mod pin_impls {
+    use crate::hal::gpio::{gpioa::PA2, gpioc::PC1, Alternate};
+
+    const AF11: u8 = 11;
+
+    unsafe impl crate::mac::MdioPin for PA2<Alternate<AF11>> {}
+    unsafe impl crate::mac::MdcPin for PC1<Alternate<AF11>> {}
+}
+
+#[cfg(feature = "stm32f1xx-hal")]
+mod pin_impls {
+    use crate::hal::gpio::{gpioa::PA2, gpioc::PC1, Alternate, PushPull};
+
+    unsafe impl crate::mac::MdioPin for PA2<Alternate<PushPull>> {}
+    unsafe impl crate::mac::MdcPin for PC1<Alternate<PushPull>> {}
+}

src/mac/miim/f_series_miim.rs

@@ -0,0 +1,59 @@
+use crate::peripherals::ETHERNET_MAC;
+use crate::stm32::ethernet_mac::MACMDIOAR;
+
+use super::{MdcPin, MdioPin};
+
+use crate::hal::gpio::{Alternate, PA2, PC1};
+
+#[inline(always)]
+fn miim_wait_ready(iar: &MACMDIOAR) {
+    while iar.read().mb().bit_is_set() {}
+}
+
+#[inline(always)]
+pub(crate) fn miim_write(eth_mac: &mut ETHERNET_MAC, phy: u8, reg: u8, data: u16) {
+    miim_wait_ready(&eth_mac.macmdioar);
+
+    eth_mac.macmdiodr.write(|w| unsafe { w.md().bits(data) });
+
+    miim_wait_ready(&eth_mac.macmdioar);
+
+    eth_mac.macmdioar.modify(|_, w| unsafe {
+        w.pa()
+            .bits(phy)
+            .rda()
+            .bits(reg)
+            /* Write operation GOC=01*/
+            .goc()
+            .variant(0b01)
+            .mb()
+            .set_bit()
+    });
+
+    miim_wait_ready(&eth_mac.macmdioar);
+}
+
+#[inline(always)]
+pub(crate) fn miim_read(eth_mac: &mut ETHERNET_MAC, phy: u8, reg: u8) -> u16 {
+    miim_wait_ready(&eth_mac.macmdioar);
+
+    eth_mac.macmdioar.modify(|_, w| unsafe {
+        w.pa()
+            .bits(phy)
+            .rda()
+            .bits(reg)
+            /* Write operation GOC=11*/
+            .goc()
+            .variant(0b11)
+            .mb()
+            .set_bit()
+    });
+
+    miim_wait_ready(&eth_mac.macmdioar);
+
+    // Return value:
+    eth_mac.macmdiodr.read().md().bits()
+}
+
+unsafe impl MdcPin for PC1<Alternate<11>> {}
+unsafe impl MdioPin for PA2<Alternate<11>> {}