Add MIIM support to H7

datdenkikniet · datdenkikniet · commit df931cc4aec8 · 2023-02-08T23:08:48.000+01:00
diff --git a/examples/arp.rs b/examples/arp.rs
@@ -21,9 +21,6 @@ use stm32_eth::{
     Parts, MTU,
 };
 
-#[cfg(feature = "f-series")]
-use stm32_eth::mac::{phy::BarePhy, Phy};
-
 pub mod common;
 
 use stm32_eth::dma::{RxDescriptorRing, TxDescriptorRing, TxError};
diff --git a/examples/common.rs b/examples/common.rs
@@ -377,8 +377,8 @@ mod pins {
 
     pub type Pps = PB5<Output<PushPull>>;
 
-    pub type Mdio = ();
-    pub type Mdc = ();
+    pub type Mdio = PA2<Alternate<11>>;
+    pub type Mdc = PC1<Alternate<11>>;
 
     pub fn setup_pins(
         gpio: Gpio,
@@ -403,8 +403,8 @@ mod pins {
         let tx_d0 = gpiog.pg13.into_input();
         let tx_d1 = gpiob.pb13.into_input();
 
-        let mdc = ();
-        let mdio = ();
+        let mdio = gpioa.pa2.into_alternate();
+        let mdc = gpioc.pc1.into_alternate();
 
         let pps = gpiob.pb5.into_push_pull_output();
 
diff --git a/examples/rtic-timestamp.rs b/examples/rtic-timestamp.rs
@@ -82,15 +82,14 @@ mod app {
         defmt::info!("Configuring ethernet");
 
         let Parts { dma, mac, mut ptp } =
-            stm32_eth::new(ethernet, rx_ring, tx_ring, clocks, pins).unwrap();
+            stm32_eth::new_with_mii(ethernet, rx_ring, tx_ring, clocks, pins, mdio, mdc).unwrap();
 
         #[cfg(not(feature = "stm32h7xx-hal"))]
         ptp.enable_pps(pps);
 
         defmt::info!("Enabling interrupts");
         dma.enable_interrupt();
 
-        #[cfg(not(feature = "stm32h7xx-hal"))]
         match EthernetPhy::from_miim(mac, 0) {
             Ok(mut phy) => {
                 defmt::info!(
diff --git a/src/lib.rs b/src/lib.rs
@@ -56,13 +56,10 @@ pub use smoltcp;
 #[cfg(feature = "device-selected")]
 use {
     dma::{DmaParts, EthernetDMA, RxDescriptorRing, TxDescriptorRing},
-    mac::{EthernetMAC, MacParts, Speed, WrongClock},
+    mac::{EthernetMAC, EthernetMACWithMii, MacParts, MdcPin, MdioPin, Speed, WrongClock},
     setup::*,
 };
 
-#[cfg(all(feature = "device-selected", feature = "f-series"))]
-use mac::{EthernetMACWithMii, MdcPin, MdioPin};
-
 #[cfg(all(feature = "device-selected", feature = "ptp"))]
 use ptp::EthernetPTP;
 
@@ -165,7 +162,7 @@ where
 /// accessible by the peripheral. Core-Coupled Memory (CCM) is
 /// usually not accessible.
 /// - HCLK must be at least 25 MHz.
-#[cfg(all(feature = "device-selected", feature = "f-series"))]
+#[cfg(all(feature = "device-selected"))]
 pub fn new_with_mii<'rx, 'tx, REFCLK, CRS, TXEN, TXD0, TXD1, RXD0, RXD1, MDIO, MDC>(
     parts: PartsIn,
     rx_buffer: RxDescriptorRing<'rx>,
@@ -194,10 +191,13 @@ where
 
     let dma_parts = DmaParts {
         eth_dma: parts.dma.into(),
+        #[cfg(feature = "stm32h7xx-hal")]
+        eth_mtl: parts.mtl,
     };
 
     let mac_parts = MacParts {
         eth_mac: parts.mac.into(),
+        #[cfg(feature = "f-series")]
         eth_mmc: parts.mmc.into(),
     };
 
@@ -206,7 +206,12 @@ where
 
     // Configure the ethernet PTP
     #[cfg(feature = "ptp")]
-    let ptp = EthernetPTP::new(parts.ptp.into(), clocks, &dma);
+    let ptp = EthernetPTP::new(
+        #[cfg(feature = "f-series")]
+        parts.ptp.into(),
+        clocks,
+        &dma,
+    );
 
     // Configure the ethernet MAC
     let mac =
diff --git a/src/mac/miim/f_series_miim.rs b/src/mac/miim/f_series_miim.rs
@@ -0,0 +1,76 @@
+use crate::peripherals::ETHERNET_MAC;
+use crate::stm32::ethernet_mac::MACMIIAR;
+
+#[inline(always)]
+fn miim_wait_ready(iar: &MACMIIAR) {
+    while iar.read().mb().bit_is_set() {}
+}
+
+#[inline(always)]
+pub(crate) fn miim_write(eth_mac: &mut ETHERNET_MAC, phy: u8, reg: u8, data: u16) {
+    miim_wait_ready(&eth_mac.macmiiar);
+    eth_mac.macmiidr.write(|w| w.md().bits(data));
+
+    miim_wait_ready(&eth_mac.macmiiar);
+
+    eth_mac.macmiiar.modify(|_, w| {
+        w.pa()
+            .bits(phy)
+            .mr()
+            .bits(reg)
+            /* Write operation MW=1*/
+            .mw()
+            .set_bit()
+            .mb()
+            .set_bit()
+    });
+    miim_wait_ready(&eth_mac.macmiiar);
+}
+
+#[inline(always)]
+pub(crate) fn miim_read(eth_mac: &mut ETHERNET_MAC, phy: u8, reg: u8) -> u16 {
+    miim_wait_ready(&eth_mac.macmiiar);
+    eth_mac.macmiiar.modify(|_, w| {
+        w.pa()
+            .bits(phy)
+            .mr()
+            .bits(reg)
+            /* Read operation MW=0 */
+            .mw()
+            .clear_bit()
+            .mb()
+            .set_bit()
+    });
+    miim_wait_ready(&eth_mac.macmiiar);
+
+    // Return value:
+    eth_mac.macmiidr.read().md().bits()
+}
+
+#[cfg(feature = "stm32f4xx-hal")]
+mod pin_impls {
+    use crate::hal::gpio::{gpioa::PA2, gpioc::PC1, Alternate};
+
+    const AF11: u8 = 11;
+
+    unsafe impl crate::mac::MdioPin for PA2<Alternate<AF11>> {}
+    unsafe impl crate::mac::MdcPin for PC1<Alternate<AF11>> {}
+}
+
+#[cfg(feature = "stm32f7xx-hal")]
+mod pin_impls {
+    use crate::hal::gpio::{gpioa::PA2, gpioc::PC1, Alternate};
+
+    const AF11: u8 = 11;
+
+    unsafe impl crate::mac::MdioPin for PA2<Alternate<AF11>> {}
+    unsafe impl crate::mac::MdcPin for PC1<Alternate<AF11>> {}
+}
+
+#[cfg(feature = "stm32f1xx-hal")]
+mod pin_impls {
+    use crate::hal::gpio::{gpioa::PA2, gpioc::PC1, Alternate, PushPull};
+
+    unsafe impl crate::mac::MdioPin for PA2<Alternate<PushPull>> {}
+    unsafe impl crate::mac::MdcPin for PC1<Alternate<PushPull>> {}
+}
diff --git a/src/mac/miim/h_miim.rs b/src/mac/miim/h_miim.rs
@@ -0,0 +1,59 @@
+use crate::peripherals::ETHERNET_MAC;
+use crate::stm32::ethernet_mac::MACMDIOAR;
+
+use super::{MdcPin, MdioPin};
+
+use crate::hal::gpio::{Alternate, PA2, PC1};
+
+#[inline(always)]
+fn miim_wait_ready(iar: &MACMDIOAR) {
+    while iar.read().mb().bit_is_set() {}
+}
+
+#[inline(always)]
+pub(crate) fn miim_write(eth_mac: &mut ETHERNET_MAC, phy: u8, reg: u8, data: u16) {
+    miim_wait_ready(&eth_mac.macmdioar);
+
+    eth_mac.macmdiodr.write(|w| unsafe { w.md().bits(data) });
+
+    miim_wait_ready(&eth_mac.macmdioar);
+
+    eth_mac.macmdioar.modify(|_, w| unsafe {
+        w.pa()
+            .bits(phy)
+            .rda()
+            .bits(reg)
+            /* Write operation GOC=01*/
+            .goc()
+            .variant(0b01)
+            .mb()
+            .set_bit()
+    });
+
+    miim_wait_ready(&eth_mac.macmdioar);
+}
+
+#[inline(always)]
+pub(crate) fn miim_read(eth_mac: &mut ETHERNET_MAC, phy: u8, reg: u8) -> u16 {
+    miim_wait_ready(&eth_mac.macmdioar);
+
+    eth_mac.macmdioar.modify(|_, w| unsafe {
+        w.pa()
+            .bits(phy)
+            .rda()
+            .bits(reg)
+            /* Write operation GOC=11*/
+            .goc()
+            .variant(0b11)
+            .mb()
+            .set_bit()
+    });
+
+    miim_wait_ready(&eth_mac.macmdioar);
+
+    // Return value:
+    eth_mac.macmdiodr.read().md().bits()
+}
+
+unsafe impl MdcPin for PC1<Alternate<11>> {}
+unsafe impl MdioPin for PA2<Alternate<11>> {}
diff --git a/src/mac/miim/mod.rs b/src/mac/miim/mod.rs
@@ -3,10 +3,18 @@ pub use ieee802_3_miim::*;
 
 use core::ops::{Deref, DerefMut};
 
-use crate::{peripherals::ETHERNET_MAC, stm32::ethernet_mac::MACMIIAR};
-
 use super::EthernetMAC;
 
+#[cfg(feature = "f-series")]
+mod f_series_miim;
+#[cfg(feature = "f-series")]
+use f_series_miim::{miim_read, miim_write};
+
+#[cfg(feature = "stm32h7xx-hal")]
+mod h_miim;
+#[cfg(feature = "stm32h7xx-hal")]
+use h_miim::{miim_read, miim_write};
+
 /// MDIO pin types.
 ///
 /// # Safety
@@ -21,52 +29,6 @@ pub unsafe trait MdioPin {}
 /// may implement this trait
 pub unsafe trait MdcPin {}
 
-#[inline(always)]
-fn miim_wait_ready(iar: &MACMIIAR) {
-    while iar.read().mb().bit_is_set() {}
-}
-
-#[inline(always)]
-fn miim_write(eth_mac: &mut ETHERNET_MAC, phy: u8, reg: u8, data: u16) {
-    miim_wait_ready(&eth_mac.macmiiar);
-    eth_mac.macmiidr.write(|w| w.md().bits(data));
-
-    miim_wait_ready(&eth_mac.macmiiar);
-
-    eth_mac.macmiiar.modify(|_, w| {
-        w.pa()
-            .bits(phy)
-            .mr()
-            .bits(reg)
-            /* Write operation MW=1*/
-            .mw()
-            .set_bit()
-            .mb()
-            .set_bit()
-    });
-    miim_wait_ready(&eth_mac.macmiiar);
-}
-
-#[inline(always)]
-fn miim_read(eth_mac: &mut ETHERNET_MAC, phy: u8, reg: u8) -> u16 {
-    miim_wait_ready(&eth_mac.macmiiar);
-    eth_mac.macmiiar.modify(|_, w| {
-        w.pa()
-            .bits(phy)
-            .mr()
-            .bits(reg)
-            /* Read operation MW=0 */
-            .mw()
-            .clear_bit()
-            .mb()
-            .set_bit()
-    });
-    miim_wait_ready(&eth_mac.macmiiar);
-
-    // Return value:
-    eth_mac.macmiidr.read().md().bits()
-}
-
 /// Serial Management Interface
 ///
 /// Borrows an [`EthernetMAC`] and holds a mutable borrow to the SMI pins.
@@ -120,34 +82,6 @@ where
     }
 }
 
-#[cfg(feature = "stm32f4xx-hal")]
-mod pin_impls {
-    use crate::hal::gpio::{gpioa::PA2, gpioc::PC1, Alternate};
-
-    const AF11: u8 = 11;
-
-    unsafe impl super::MdioPin for PA2<Alternate<AF11>> {}
-    unsafe impl super::MdcPin for PC1<Alternate<AF11>> {}
-}
-
-#[cfg(feature = "stm32f7xx-hal")]
-mod pin_impls {
-    use crate::hal::gpio::{gpioa::PA2, gpioc::PC1, Alternate};
-
-    const AF11: u8 = 11;
-
-    unsafe impl super::MdioPin for PA2<Alternate<AF11>> {}
-    unsafe impl super::MdcPin for PC1<Alternate<AF11>> {}
-}
-
-#[cfg(feature = "stm32f1xx-hal")]
-mod pin_impls {
-    use crate::hal::gpio::{gpioa::PA2, gpioc::PC1, Alternate, PushPull};
-
-    unsafe impl super::MdioPin for PA2<Alternate<PushPull>> {}
-    unsafe impl super::MdcPin for PC1<Alternate<PushPull>> {}
-}
-
 /// Ethernet media access control (MAC) with owned MII
 ///
 /// This version of the struct owns it's MII pins,
diff --git a/src/mac/mod.rs b/src/mac/mod.rs
