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Commit d716770

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Slight cleanup
1 parent 8738c3c commit d716770

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2 files changed

+6
-2
lines changed

2 files changed

+6
-2
lines changed

examples/async-rtic-timestamp.rs

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,10 @@ mod common;
3838

3939
extern crate async_rtic as rtic;
4040

41+
defmt::timestamp!("{=u64:us}", {
42+
(stm32_eth::ptp::EthernetPTP::now().total_nanos() / 1_000) as u64
43+
});
44+
4145
#[rtic::app(device = stm32_eth::stm32, dispatchers = [SPI1])]
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mod app {
4347

@@ -159,7 +163,7 @@ mod app {
159163
continue;
160164
};
161165

162-
defmt::debug!("RX timestamp: {}", rx_timestamp);
166+
defmt::info!("RX timestamp: {}", rx_timestamp);
163167

164168
if dst_mac == [0xAB, 0xCD, 0xEF, 0x12, 0x34, 0x56] {
165169
let mut timestamp_data = [0u8; 8];

src/dma/rx/mod.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -285,7 +285,7 @@ impl<'a> RxRing<'a> {
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/// Receive the next packet (if any is ready), or return [`Err`]
286286
/// immediately.
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pub fn recv_next(&mut self, packet_id: Option<PacketId>) -> Result<RxPacket, RxError> {
288-
let entry = self.recv_next_impl(packet_id.map(|p| p.into()))?;
288+
let entry = self.recv_next_impl(packet_id)?;
289289

290290
Ok(self.recv_and_timestamp(entry))
291291
}

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