File tree Expand file tree Collapse file tree 1 file changed +10
-2
lines changed Expand file tree Collapse file tree 1 file changed +10
-2
lines changed Original file line number Diff line number Diff line change @@ -415,7 +415,6 @@ impl EthernetPTP {
415
415
is_tsint
416
416
}
417
417
418
- #[ cfg( feature = "f-series" ) ]
419
418
/// Configure the PPS output frequency.
420
419
///
421
420
/// The PPS output frequency becomes `2 ^ pps_freq`. `pps_freq` is
@@ -426,10 +425,19 @@ impl EthernetPTP {
426
425
// SAFETY: we atomically write to the PTPPPSCR register, which is
427
426
// not read or written to anywhere else. The SVD files are incorrectly
428
427
// saying that the bits in this register are read-only.
428
+ #[ cfg( feature = "f-series" ) ]
429
429
unsafe {
430
430
let ptpppscr = self . eth_ptp . ptpppscr . as_ptr ( ) as * mut u32 ;
431
431
core:: ptr:: write_volatile ( ptpppscr, pps_freq as u32 ) ;
432
432
}
433
+
434
+ #[ cfg( feature = "stm32h7xx-hal" ) ]
435
+ {
436
+ // SAFETY: we only access and modify the `macppscr` (PPS Control register)
437
+ let macppscr = unsafe { & self . mac ( ) . macppscr } ;
438
+
439
+ macppscr. modify ( |_, w| w. ppsctrl ( ) . variant ( pps_freq) ) ;
440
+ }
433
441
}
434
442
}
435
443
@@ -442,7 +450,7 @@ mod test {
442
450
// with the provided clock speeds.
443
451
#[ test]
444
452
fn hclk_to_regs ( ) {
445
- for hclk_hz in ( 25 ..180 ) . map ( |v| v * 1_000_000 ) {
453
+ for hclk_hz in ( 25 ..480 ) . map ( |v| v * 1_000_000 ) {
446
454
let ( stssi, tsa) = EthernetPTP :: calculate_regs ( hclk_hz) ;
447
455
448
456
let stssi = stssi. raw ( ) as f64 ;
You can’t perform that action at this time.
0 commit comments