Fix async receive and timestamping on h7, it's wonky

Author: datdenkikniet

src/dma/mod.rs

@@ -298,6 +298,8 @@ impl<'rx, 'tx> EthernetDMA<'rx, 'tx> {
         let rx_descriptor_addr = eth_dma.dmaccarx_dr.read().bits();
         let rx_buffer_addr = eth_dma.dmaccarx_br.read().bits();
 
+        // TODO: add a link to a/the github issue describing this problem,
+        // and how to solve it.
         panic!("Fatal bus error! Is the descriptor and buffer memory accessible by the Ethernet MAC/DMA? TXDESC: {:08X}, TXBUF: {:08X}, RXDESC: {:08X}, TXDESC: {:08X}", tx_descriptor_addr, tx_buffer_addr, rx_descriptor_addr, rx_buffer_addr);
     }
 
@@ -352,9 +354,6 @@ impl<'rx, 'tx> EthernetDMA<'rx, 'tx> {
             });
 
             if status.fbe().bit_is_set() {
-                // TODO: add a link to a/the github issue describing this problem,
-                // and how to solve it.
-
                 EthernetDMA::panic_fbe();
             }
 

src/dma/rx/mod.rs

@@ -216,11 +216,14 @@ impl<'a> RxRing<'a> {
         self.ring.descriptor(self.next_entry).is_available()
     }
 
-    /// Receive the next packet (if any is ready).
+    /// Obtain the index of the packet to receive (if any is ready).
     ///
-    /// This function returns a tuple of `Ok((entry_index, length))` on
+    /// This function returns a tuple of `Ok(entry_index)` on
     /// success. Whoever receives the `Ok` must ensure that `set_owned`
     /// is eventually called on the entry with that index.
+    ///
+    /// Actually obtaining the relevant RxPacket is done using
+    /// [`RxRing::recv_and_timestamp`].
     fn recv_next_impl(
         &mut self,
         // NOTE(allow): packet_id is unused if ptp is disabled.
@@ -245,14 +248,10 @@ impl<'a> RxRing<'a> {
         }
     }
 
-    /// Receive the next packet (if any is ready), or return [`Err`]
-    /// immediately.
-    pub fn recv_next(&mut self, packet_id: Option<PacketId>) -> Result<RxPacket, RxError> {
+    fn recv_and_timestamp(&mut self, entry: usize) -> RxPacket {
         #[cfg(feature = "stm32h7xx-hal")]
         let entries_len = self.ring.len();
 
-        let entry = self.recv_next_impl(packet_id.map(|p| p.into()))?;
-
         #[cfg(feature = "f-series")]
         let (desc, buffer) = self.ring.get_mut(entry);
 
@@ -276,11 +275,19 @@ impl<'a> RxRing<'a> {
 
         let length = desc.frame_len();
 
-        Ok(RxPacket {
+        RxPacket {
             entry: desc,
             buffer,
             length,
-        })
+        }
+    }
+
+    /// Receive the next packet (if any is ready), or return [`Err`]
+    /// immediately.
+    pub fn recv_next(&mut self, packet_id: Option<PacketId>) -> Result<RxPacket, RxError> {
+        let entry = self.recv_next_impl(packet_id.map(|p| p.into()))?;
+
+        Ok(self.recv_and_timestamp(entry))
     }
 
     /// Receive the next packet.
@@ -302,14 +309,7 @@ impl<'a> RxRing<'a> {
         })
         .await;
 
-        let (desc, buffer) = self.ring.get_mut(entry);
-        let length = desc.frame_len();
-
-        RxPacket {
-            entry: desc,
-            buffer,
-            length,
-        }
+        self.recv_and_timestamp(entry)
     }
 }