Update dependencies

Author: Wojciech Ogórek

Cargo.toml

@@ -18,20 +18,20 @@ maintenance = { status = "experimental" }
 features = [ "smoltcp-phy", "stm32f429" ]
 
 [dependencies]
-volatile-register = "0.2"
-aligned = "0.3"
-stm32f1xx-hal = {version = "0.7.0", optional = true}
-stm32f7xx-hal = {version = "0.2.0", optional = true}
-stm32f4xx-hal = {version = "0.8.3", optional = true}
-cortex-m = "0.6.2"
-log = { version = "0.4", optional = true }
+volatile-register = "0.2.1"
+aligned = "0.4.0"
+stm32f1xx-hal = { version = "0.9.0", optional = true }
+stm32f7xx-hal = { version = "0.6.0", optional = true }
+stm32f4xx-hal = { version = "0.12.0", optional = true }
+cortex-m = "0.7.4"
+log = { version = "0.4.14", optional = true }
 
 [dependencies.smoltcp]
-version = "0.7.0"
+version = "0.8.0"
 # git = "https://github.com/smoltcp-rs/smoltcp"
 # branch = "master"
 default-features = false
-features = ["ethernet", "proto-ipv4"]
+features = ["medium-ethernet", "proto-ipv4"]
 optional = true
 
 [features]
@@ -62,13 +62,13 @@ stm32f779 = ["stm32f7xx-hal/stm32f779", "device-selected", "fence"]
 smoltcp-phy = ["smoltcp"]
 
 [dev-dependencies]
-cortex-m = "0.6.2"
-cortex-m-rt = "0.6"
-panic-itm = "0.4"
-panic-rtt-target = { version = "0.1", features = ["cortex-m"] }
-rtt-target = { version = "0.2.0", features = ["cortex-m"] }
-cortex-m-semihosting = "0.3.5"
-stm32f1xx-hal = {version = "0.6.1", features = ["rt"] }
+cortex-m = "0.7.4"
+cortex-m-rt = "0.7.1"
+panic-itm = "0.4.2"
+panic-rtt-target = { version = "0.1.2", features = ["cortex-m"] }
+rtt-target = { version = "0.3.1", features = ["cortex-m"] }
+cortex-m-semihosting = "0.3.7"
+stm32f1xx-hal = { version = "0.9.0", features = ["rt"] }
 #stm32f4xx-hal = {version = "0.8.3", features = ["rt"] }
 
 [[example]]

src/lib.rs

@@ -137,7 +137,7 @@ impl<'rx, 'tx> Eth<'rx, 'tx> {
     }
 
     fn init(&mut self, clocks: Clocks) -> Result<(), WrongClock> {
-        let clock_range = match clocks.hclk().0 {
+        let clock_range = match clocks.hclk().to_Hz() {
             0..=24_999_999 => return Err(WrongClock),
             25_000_000..=34_999_999 => ETH_MACMIIAR_CR_HCLK_DIV_16,
             35_000_000..=59_999_999 => ETH_MACMIIAR_CR_HCLK_DIV_26,

src/rx.rs

@@ -234,9 +234,7 @@ impl<'a> RxRing<'a> {
         // Register RxDescriptor
         eth_dma.dmardlar.write(|w| {
             // Note: unsafe block required for `stm32f107`.
-            unsafe {
-                w.srl().bits(ring_ptr as u32)
-            }
+            unsafe { w.srl().bits(ring_ptr as u32) }
         });
 
         // We already have fences in `set_owned`, which is called in `setup`

src/setup.rs

@@ -140,7 +140,6 @@ pub(crate) fn setup() {
             while rcc.ahbenr.read().dma2en().is_disabled() {}
         }
     });
-
 }
 
 /// RMII Reference Clock.
@@ -239,7 +238,10 @@ macro_rules! impl_pins {
     };
 }
 
-#[cfg(all(feature = "device-selected", any(feature = "stm32f4xx-hal", feature = "stm32f7xx-hal")))]
+#[cfg(all(
+    feature = "device-selected",
+    any(feature = "stm32f4xx-hal", feature = "stm32f7xx-hal")
+))]
 impl_pins!(
     RmiiRefClk: [
         PA1<Input<Floating>>,
@@ -276,9 +278,7 @@ impl_pins!(
 #[cfg(feature = "stm32f1xx-hal")]
 mod stm32f1 {
     use super::*;
-    use stm32f1xx_hal::gpio::{
-        gpioa, gpiob, gpioc, gpiod, Alternate, Floating, Input, PushPull,
-    };
+    use stm32f1xx_hal::gpio::{gpioa, gpiob, gpioc, gpiod, Alternate, Floating, Input, PushPull};
 
     // STM32F1xx's require access to the CRL/CRH registers to change pin mode. As a result, we
     // require that pins are already in the necessary mode before constructing `EthPins` as it