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Fix read_and_clear logic for h7
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+19
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src/ptp/mod.rs

Lines changed: 19 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -433,9 +433,17 @@ impl EthernetPTP {
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}
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#[cfg(feature = "stm32h7xx-hal")]
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{
436-
// SAFETY: we only modify the ethernet ptp status register.
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// SAFETY: we only read the ethernet ptp status register.
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let mac = unsafe { Self::mac() };
438-
mac.mactssr.read().tstargt0().bit_is_set()
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// Reading the register clears all of the bits in
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// that register.
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let tssr = mac.mactssr.read();
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let tstargt0 = tssr.tstargt0().bit_is_set();
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let tstrgterr0 = tssr.tstrgterr0().bit_is_set();
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tstargt0 || tstrgterr0
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}
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}
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@@ -459,18 +467,18 @@ impl EthernetPTP {
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#[cfg(feature = "stm32h7xx-hal")]
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let is_tsint = {
462-
// SAFETY: we only write to `mactssr` (Timestamp Status register)
463-
let mactssr = unsafe { &Self::mac().mactssr };
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// Reading the bit clears it, and deasserts the interrupt.
466-
mactssr.read().tstargt0().bit_is_set()
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// SAFETY: we only read from `macisr` (Interrupt status register)
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let macisr = unsafe { &Self::mac().macisr };
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macisr.read().tsis().bit_is_set()
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};
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#[cfg(feature = "async-await")]
470-
if let Some(waker) = EthernetPTP::waker().take() {
471-
waker.wake();
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} else {
473-
EthernetPTP::read_and_clear_interrupt_flag();
476+
if is_tsint {
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if let Some(waker) = EthernetPTP::waker().take() {
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waker.wake();
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} else {
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EthernetPTP::read_and_clear_interrupt_flag();
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}
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}
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#[cfg(not(feature = "async-await"))]

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