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franeklubifraneklubi
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Fix all examples
1 parent 3eb5f92 commit 34cf14a

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6 files changed

+82
-129
lines changed

6 files changed

+82
-129
lines changed

‎Cargo.toml

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -65,8 +65,7 @@ cortex-m = "0.7.4"
6565
cortex-m-rt = "0.7.1"
6666
panic-itm = "0.4.2"
6767
cortex-m-semihosting = "0.3.7"
68-
stm32f4xx-hal = { version = "0.12.0", features = ["rt"] }
69-
# stm32f1xx-hal = { version = "0.9.0", features = ["rt"] }
68+
fugit = "0.3.5"
7069

7170
[[example]]
7271
name = "pktgen"
@@ -79,9 +78,12 @@ required-features = [
7978
"smoltcp/log", "smoltcp/verbose"
8079
]
8180

82-
# [[example]]
83-
# name = "ip-f107"
84-
# required-features = ["stm32f107", "smi", "smoltcp-phy", "smoltcp/socket-tcp"]
81+
[[example]]
82+
name = "ip-f107"
83+
required-features = [
84+
"stm32f107", "smoltcp-phy", "log", "smoltcp/socket-tcp", "smoltcp/socket-icmp",
85+
"smoltcp/log", "smoltcp/verbose"
86+
]
8587

8688
[[example]]
8789
name = "arp"

‎examples/arp-smoltcp.rs

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -12,24 +12,23 @@ extern crate panic_itm;
1212

1313
use core::cell::RefCell;
1414
use core::default::Default;
15-
use cortex_m_rt::{entry, exception};
1615

1716
use cortex_m::asm;
1817
use cortex_m::interrupt::Mutex;
18+
use cortex_m_rt::{entry, exception};
19+
use cortex_m_semihosting::hprintln;
20+
use fugit::RateExtU32;
21+
use smoltcp::wire::{
22+
ArpOperation, ArpPacket, ArpRepr, EthernetAddress, EthernetFrame, EthernetProtocol,
23+
EthernetRepr, Ipv4Address,
24+
};
1925
use stm32_eth::{
2026
hal::gpio::{GpioExt, Speed},
2127
hal::rcc::RccExt,
22-
hal::time::U32Ext,
28+
// hal::time::U32Ext,
2329
smi,
2430
stm32::{interrupt, CorePeripherals, Peripherals, SYST},
2531
};
26-
27-
use cortex_m_semihosting::hprintln;
28-
29-
use smoltcp::wire::{
30-
ArpOperation, ArpPacket, ArpRepr, EthernetAddress, EthernetFrame, EthernetProtocol,
31-
EthernetRepr, Ipv4Address,
32-
};
3332
use stm32_eth::{Eth, EthPins, RingEntry, TxError};
3433

3534
const PHY_REG_BSR: u8 = 0x01;
@@ -47,7 +46,7 @@ fn main() -> ! {
4746

4847
let rcc = p.RCC.constrain();
4948
// HCLK must be at least 25MHz to use the ethernet peripheral
50-
let clocks = rcc.cfgr.sysclk(32.mhz()).hclk(32.mhz()).freeze();
49+
let clocks = rcc.cfgr.sysclk(32.MHz()).hclk(32.MHz()).freeze();
5150

5251
setup_systick(&mut cp.SYST);
5352

‎examples/arp.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,10 +16,10 @@ use cortex_m_rt::{entry, exception};
1616

1717
use cortex_m::asm;
1818
use cortex_m::interrupt::Mutex;
19+
use fugit::RateExtU32;
1920
use stm32_eth::{
2021
hal::gpio::{GpioExt, Speed},
2122
hal::rcc::RccExt,
22-
hal::time::U32Ext,
2323
smi,
2424
stm32::{interrupt, CorePeripherals, Peripherals, SYST},
2525
};
@@ -43,7 +43,7 @@ fn main() -> ! {
4343

4444
let rcc = p.RCC.constrain();
4545
// HCLK must be at least 25MHz to use the ethernet peripheral
46-
let clocks = rcc.cfgr.sysclk(32.mhz()).hclk(32.mhz()).freeze();
46+
let clocks = rcc.cfgr.sysclk(32.MHz()).hclk(32.MHz()).freeze();
4747

4848
setup_systick(&mut cp.SYST);
4949

‎examples/ip-f107.rs

Lines changed: 60 additions & 108 deletions
Original file line numberDiff line numberDiff line change
@@ -3,30 +3,49 @@
33
#![no_std]
44
#![no_main]
55

6-
use panic_rtt_target as _;
6+
extern crate panic_itm;
77

88
use cortex_m::asm;
99
use cortex_m_rt::{entry, exception};
1010
use stm32_eth::{
11+
hal::flash::FlashExt,
1112
hal::gpio::GpioExt,
1213
hal::rcc::RccExt,
1314
stm32::{interrupt, CorePeripherals, Peripherals, SYST},
14-
RxDescriptor, TxDescriptor,
1515
};
1616

1717
use core::cell::RefCell;
1818
use cortex_m::interrupt::Mutex;
1919

2020
use core::fmt::Write;
21+
use cortex_m_semihosting::hio;
2122

22-
use smoltcp::iface::{EthernetInterfaceBuilder, NeighborCache};
23-
use smoltcp::socket::{SocketSet, TcpSocket, TcpSocketBuffer};
23+
use fugit::RateExtU32;
24+
use log::{Level, LevelFilter, Metadata, Record};
25+
use smoltcp::iface::{InterfaceBuilder, NeighborCache};
26+
use smoltcp::socket::{TcpSocket, TcpSocketBuffer};
2427
use smoltcp::time::Instant;
2528
use smoltcp::wire::{EthernetAddress, IpAddress, IpCidr, Ipv4Address};
26-
use stm32_eth::{Eth, EthPins, PhyAddress, RingEntry};
2729

28-
use rtt_target::{rprintln, rtt_init_print};
29-
use stm32f1xx_hal::{flash::FlashExt, prelude::*};
30+
use stm32_eth::{Eth, EthPins, RingEntry};
31+
32+
static mut LOGGER: HioLogger = HioLogger {};
33+
34+
struct HioLogger {}
35+
36+
impl log::Log for HioLogger {
37+
fn enabled(&self, metadata: &Metadata) -> bool {
38+
metadata.level() <= Level::Trace
39+
}
40+
41+
fn log(&self, record: &Record) {
42+
if self.enabled(record.metadata()) {
43+
let mut stdout = hio::hstdout().unwrap();
44+
writeln!(stdout, "{} - {}", record.level(), record.args()).unwrap();
45+
}
46+
}
47+
fn flush(&self) {}
48+
}
3049

3150
const SRC_MAC: [u8; 6] = [0x00, 0x00, 0xDE, 0xAD, 0xBE, 0xEF];
3251

@@ -35,91 +54,39 @@ static ETH_PENDING: Mutex<RefCell<bool>> = Mutex::new(RefCell::new(false));
3554

3655
#[entry]
3756
fn main() -> ! {
38-
rtt_init_print!();
57+
unsafe {
58+
log::set_logger(&LOGGER).unwrap();
59+
}
60+
log::set_max_level(LevelFilter::Info);
3961

40-
let p = stm32f1xx_hal::stm32::Peripherals::take().unwrap();
62+
let mut stdout = hio::hstdout().unwrap();
63+
64+
let p = Peripherals::take().unwrap();
4165
let mut cp = CorePeripherals::take().unwrap();
4266

4367
let mut flash = p.FLASH.constrain();
4468

69+
let rcc = p.RCC.constrain();
4570
// HCLK must be at least 25MHz to use the ethernet peripheral
46-
rprintln!("Setting up clocks");
47-
48-
// Code below handle situation when ethernet controller has its own clock
49-
50-
// let mut rcc = p.RCC.constrain();
51-
// let clocks = rcc
52-
// .cfgr
53-
// .use_hse(8.mhz())
54-
// .sysclk(72.mhz())
55-
// .hclk(72.mhz())
56-
// .pclk1(36.mhz())
57-
// .freeze(&mut flash.acr);
58-
///////////////////////////////////////////////////////////////////////////////
59-
60-
// This case handles case when ethernet controller clock is connected to MCO pin of STM32F107
61-
// MCU has connected 25 MHz oscillator to XTAL
62-
// Prescaller valuses (see clock diagram for STM32F107)
63-
// PREDIV2 = /5
64-
// PLL2MUL = x8
65-
// PREDIV1 = /5 (We have 8 Mhz for 'Clock from PREDIV1')
66-
// PLL3MUL = x10
67-
// PREDIV1SRC = PPL2
68-
let rcc = p.RCC;
69-
rcc.cfgr2.write(|w| {
70-
w.prediv2()
71-
.div5()
72-
.pll2mul()
73-
.mul8()
74-
.prediv1src()
75-
.pll2()
76-
.prediv1()
77-
.div5()
78-
.pll3mul()
79-
.mul10()
80-
});
81-
82-
// enable HSE and wait for it to be ready
83-
rcc.cr.modify(|_, w| w.hseon().set_bit());
84-
while rcc.cr.read().hserdy().bit_is_clear() {}
85-
86-
// enable PLL2 and wait until ready
87-
rcc.cr.modify(|_, w| w.pll2on().set_bit());
88-
while rcc.cr.read().pll2rdy().bit_is_clear() {}
89-
90-
// enable PLL3 and wait until ready
91-
rcc.cr.modify(|_, w| w.pll3on().set_bit());
92-
while rcc.cr.read().pll3rdy().bit_is_clear() {}
93-
94-
// Get PLL3 clock on PA8 pin (MCO)
95-
rcc.cfgr.modify(|_, w| w.mco().pll3ethernet());
96-
97-
let mut rcc = rcc.constrain();
98-
let acr = &mut flash.acr;
99-
10071
let clocks = rcc
10172
.cfgr
102-
.use_hse(8.mhz()) // HSE (Clock from PREDIV1), PLL configuration PREDIV2/PLL2MUL changes 25Mhz to 8Mhz
103-
.sysclk(72.mhz())
104-
.pclk1(36.mhz())
105-
.freeze(acr);
106-
///////////////////////////////////////////////////////////////////////////////
73+
.sysclk(32.MHz())
74+
.hclk(32.MHz())
75+
.freeze(&mut flash.acr);
10776

108-
rprintln!("Setting up systick");
10977
setup_systick(&mut cp.SYST);
11078

111-
//writeln!(stdout, "Enabling ethernet...").unwrap();
112-
let mut gpioa = p.GPIOA.split(&mut rcc.apb2);
113-
let mut gpiob = p.GPIOB.split(&mut rcc.apb2);
114-
let mut gpioc = p.GPIOC.split(&mut rcc.apb2);
79+
writeln!(stdout, "Enabling ethernet...").unwrap();
80+
81+
let mut gpioa = p.GPIOA.split();
82+
let mut gpiob = p.GPIOB.split();
83+
let mut gpioc = p.GPIOC.split();
11584

11685
// PLL3CLK goes to MCO (Main Clock Output) (PA8)
11786
let _mco = gpioa.pa8.into_alternate_push_pull(&mut gpioa.crh);
11887

11988
let ref_clk = gpioa.pa1.into_floating_input(&mut gpioa.crl);
120-
let md_io = gpioa.pa2.into_alternate_push_pull(&mut gpioa.crl);
12189
let crs = gpioa.pa7.into_floating_input(&mut gpioa.crl);
122-
let md_clk = gpioc.pc1.into_alternate_push_pull(&mut gpioc.crl);
12390
let tx_en = gpiob.pb11.into_alternate_push_pull(&mut gpiob.crh);
12491
let tx_d0 = gpiob.pb12.into_alternate_push_pull(&mut gpiob.crh);
12592
let tx_d1 = gpiob.pb13.into_alternate_push_pull(&mut gpiob.crh);
@@ -128,8 +95,6 @@ fn main() -> ! {
12895

12996
let eth_pins = EthPins {
13097
ref_clk,
131-
md_io,
132-
md_clk,
13398
crs,
13499
tx_en,
135100
tx_d0,
@@ -138,42 +103,29 @@ fn main() -> ! {
138103
rx_d1,
139104
};
140105

141-
rprintln!("Constructing `Eth`");
142-
let mut rx_ring: [RingEntry<_>; 8] = [
143-
RingEntry::<RxDescriptor>::new(),
144-
RingEntry::<RxDescriptor>::new(),
145-
RingEntry::<RxDescriptor>::new(),
146-
RingEntry::<RxDescriptor>::new(),
147-
RingEntry::<RxDescriptor>::new(),
148-
RingEntry::<RxDescriptor>::new(),
149-
RingEntry::<RxDescriptor>::new(),
150-
RingEntry::<RxDescriptor>::new(),
151-
];
152-
let mut tx_ring: [RingEntry<_>; 2] = [
153-
RingEntry::<TxDescriptor>::new(),
154-
RingEntry::<TxDescriptor>::new(),
155-
];
106+
let mut rx_ring: [RingEntry<_>; 8] = Default::default();
107+
let mut tx_ring: [RingEntry<_>; 2] = Default::default();
156108
let mut eth = Eth::new(
157109
p.ETHERNET_MAC,
158110
p.ETHERNET_DMA,
159111
&mut rx_ring[..],
160112
&mut tx_ring[..],
161-
PhyAddress::_0,
162113
clocks,
163114
eth_pins,
164115
)
165116
.unwrap();
166117
eth.enable_interrupt();
167118

168-
rprintln!("Setting up TCP/IP");
169-
let local_addr = Ipv4Address::new(10, 101, 0, 1);
170-
let ip_addr = IpCidr::new(IpAddress::from(local_addr), 16);
119+
let local_addr = Ipv4Address::new(10, 0, 0, 1);
120+
let ip_addr = IpCidr::new(IpAddress::from(local_addr), 24);
171121
let mut ip_addrs = [ip_addr];
172122
let mut neighbor_storage = [None; 16];
173123
let neighbor_cache = NeighborCache::new(&mut neighbor_storage[..]);
174124
let ethernet_addr = EthernetAddress(SRC_MAC);
175-
let mut iface = EthernetInterfaceBuilder::new(&mut eth)
176-
.ethernet_addr(ethernet_addr)
125+
126+
let mut sockets: [_; 1] = Default::default();
127+
let mut iface = InterfaceBuilder::new(&mut eth, &mut sockets[..])
128+
.hardware_addr(ethernet_addr.into())
177129
.ip_addrs(&mut ip_addrs[..])
178130
.neighbor_cache(neighbor_cache)
179131
.finalize();
@@ -184,48 +136,48 @@ fn main() -> ! {
184136
TcpSocketBuffer::new(&mut server_rx_buffer[..]),
185137
TcpSocketBuffer::new(&mut server_tx_buffer[..]),
186138
);
187-
let mut sockets_storage = [None, None];
188-
let mut sockets = SocketSet::new(&mut sockets_storage[..]);
189-
let server_handle = sockets.add(server_socket);
139+
let server_handle = iface.add_socket(server_socket);
190140

191-
rprintln!("Ready, listening at {}", ip_addr);
141+
writeln!(stdout, "Ready, listening at {}", ip_addr).unwrap();
192142
loop {
193143
let time: u64 = cortex_m::interrupt::free(|cs| *TIME.borrow(cs).borrow());
194144
cortex_m::interrupt::free(|cs| {
195145
let mut eth_pending = ETH_PENDING.borrow(cs).borrow_mut();
196146
*eth_pending = false;
197147
});
198-
match iface.poll(&mut sockets, Instant::from_millis(time as i64)) {
148+
match iface.poll(Instant::from_millis(time as i64)) {
199149
Ok(true) => {
200-
let mut socket = sockets.get::<TcpSocket>(server_handle);
150+
let socket = iface.get_socket::<TcpSocket>(server_handle);
201151
if !socket.is_open() {
202152
socket
203153
.listen(80)
204-
.unwrap_or_else(|e| rprintln!("TCP listen error: {:?}", e));
154+
.or_else(|e| writeln!(stdout, "TCP listen error: {:?}", e))
155+
.unwrap();
205156
}
206157

207158
if socket.can_send() {
208159
write!(socket, "hello\n")
209160
.map(|_| {
210161
socket.close();
211162
})
212-
.unwrap_or_else(|e| rprintln!("TCP send error: {:?}", e));
163+
.or_else(|e| writeln!(stdout, "TCP send error: {:?}", e))
164+
.unwrap();
213165
}
214166
}
215167
Ok(false) => {
216168
// Sleep if no ethernet work is pending
217169
cortex_m::interrupt::free(|cs| {
218170
let eth_pending = ETH_PENDING.borrow(cs).borrow_mut();
219171
if !*eth_pending {
220-
// Awaken by interrupt
221172
asm::wfi();
173+
// Awaken by interrupt
222174
}
223175
});
224176
}
225177
Err(e) =>
226178
// Ignore malformed packets
227179
{
228-
rprintln!("Error: {:?}", e);
180+
writeln!(stdout, "Error: {:?}", e).unwrap()
229181
}
230182
}
231183
}

‎examples/ip.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,6 @@ use cortex_m_rt::{entry, exception};
88
use stm32_eth::{
99
hal::gpio::GpioExt,
1010
hal::rcc::RccExt,
11-
hal::time::U32Ext,
1211
stm32::{interrupt, CorePeripherals, Peripherals, SYST},
1312
};
1413

@@ -18,6 +17,7 @@ use cortex_m::interrupt::Mutex;
1817
use core::fmt::Write;
1918
use cortex_m_semihosting::hio;
2019

20+
use fugit::RateExtU32;
2121
use log::{Level, LevelFilter, Metadata, Record};
2222
use smoltcp::iface::{InterfaceBuilder, NeighborCache};
2323
use smoltcp::socket::{TcpSocket, TcpSocketBuffer};
@@ -63,7 +63,7 @@ fn main() -> ! {
6363

6464
let rcc = p.RCC.constrain();
6565
// HCLK must be at least 25MHz to use the ethernet peripheral
66-
let clocks = rcc.cfgr.sysclk(32.mhz()).hclk(32.mhz()).freeze();
66+
let clocks = rcc.cfgr.sysclk(32.MHz()).hclk(32.MHz()).freeze();
6767

6868
setup_systick(&mut cp.SYST);
6969

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