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Properly initialize rings (SRAM is not 0'd out by default!) and add
some more checks
1 parent 9b7dc07 commit 2066f70

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3 files changed

+44
-37
lines changed

3 files changed

+44
-37
lines changed

examples/arp.rs

Lines changed: 1 addition & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -33,17 +33,6 @@ const PHY_ADDR: u8 = 0;
3333
static TIME: Mutex<RefCell<usize>> = Mutex::new(RefCell::new(0));
3434
static ETH_PENDING: Mutex<RefCell<bool>> = Mutex::new(RefCell::new(false));
3535

36-
/// On H7s, the ethernet DMA does not have access to the normal ram
37-
/// so we must explicitly put them in SRAM.
38-
#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth")]
39-
static mut TX_DESCRIPTORS: [TxDescriptor; 4] = [TxDescriptor::new(); 4];
40-
#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth")]
41-
static mut TX_BUFFERS: [[u8; MTU + 2]; 4] = [[0u8; MTU + 2]; 4];
42-
#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth2")]
43-
static mut RX_DESCRIPTORS: [RxDescriptor; 4] = [RxDescriptor::new(); 4];
44-
#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth2")]
45-
static mut RX_BUFFERS: [[u8; MTU + 2]; 4] = [[0u8; MTU + 2]; 4];
46-
4736
#[entry]
4837
fn main() -> ! {
4938
let p = Peripherals::take().unwrap();
@@ -57,8 +46,7 @@ fn main() -> ! {
5746

5847
let (eth_pins, mdio, mdc, _) = common::setup_pins(gpio);
5948

60-
let rx_ring = RxDescriptorRing::new(unsafe { &mut RX_DESCRIPTORS }, unsafe { &mut RX_BUFFERS });
61-
let tx_ring = TxDescriptorRing::new(unsafe { &mut TX_DESCRIPTORS }, unsafe { &mut TX_BUFFERS });
49+
let (tx_ring, rx_ring) = crate::common::setup_rings();
6250

6351
let Parts {
6452
mut dma,

examples/common.rs

Lines changed: 32 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,13 @@
44
//!
55
//! Note that this module isn't an example by itself.
66
7-
use stm32_eth::{hal::gpio::GpioExt, PartsIn};
7+
use core::mem::MaybeUninit;
8+
9+
use stm32_eth::{
10+
dma::{RxDescriptor, RxDescriptorRing, TxDescriptor, TxDescriptorRing},
11+
hal::gpio::GpioExt,
12+
PartsIn, MTU,
13+
};
814

915
#[cfg(feature = "f-series")]
1016
use stm32_eth::hal::rcc::Clocks;
@@ -17,6 +23,31 @@ pub use pins::{setup_pins, Gpio};
1723
use fugit::RateExtU32;
1824
use stm32_eth::hal::rcc::RccExt;
1925

26+
/// On H7s, the ethernet DMA does not have access to the normal ram
27+
/// so we must explicitly put them in SRAM.
28+
#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth")]
29+
static mut TX_DESCRIPTORS: MaybeUninit<[TxDescriptor; 4]> = MaybeUninit::uninit();
30+
#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth")]
31+
static mut TX_BUFFERS: MaybeUninit<[[u8; MTU + 2]; 4]> = MaybeUninit::uninit();
32+
#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth2")]
33+
static mut RX_DESCRIPTORS: MaybeUninit<[RxDescriptor; 4]> = MaybeUninit::uninit();
34+
#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth2")]
35+
static mut RX_BUFFERS: MaybeUninit<[[u8; MTU + 2]; 4]> = MaybeUninit::uninit();
36+
37+
/// Set up the buffers to be used
38+
pub fn setup_rings() -> (TxDescriptorRing<'static>, RxDescriptorRing<'static>) {
39+
let tx_desc = unsafe { TX_DESCRIPTORS.write([TxDescriptor::new(); 4]) };
40+
let tx_buf = unsafe { TX_BUFFERS.write([[0u8; MTU + 2]; 4]) };
41+
42+
let rx_desc = unsafe { RX_DESCRIPTORS.write([RxDescriptor::new(); 4]) };
43+
let rx_buf = unsafe { RX_BUFFERS.write([[0u8; MTU + 2]; 4]) };
44+
45+
(
46+
TxDescriptorRing::new(tx_desc, tx_buf),
47+
RxDescriptorRing::new(rx_desc, rx_buf),
48+
)
49+
}
50+
2051
/// Setup the clocks and return clocks and a GPIO struct that
2152
/// can be used to set up all of the pins.
2253
///

examples/rtic-timestamp.rs

Lines changed: 11 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -65,27 +65,13 @@ mod app {
6565
#[monotonic(binds = SysTick, default = true)]
6666
type Monotonic = Systick<1000>;
6767

68-
/// On H7s, the ethernet DMA does not have access to the normal ram
69-
/// so we must explicitly put them in SRAM.
70-
#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth")]
71-
static mut TX_DESCRIPTORS: [TxDescriptor; 4] = [TxDescriptor::new(); 4];
72-
#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth")]
73-
static mut TX_BUFFERS: [[u8; MTU + 2]; 4] = [[0u8; MTU + 2]; 4];
74-
#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth2")]
75-
static mut RX_DESCRIPTORS: [RxDescriptor; 4] = [RxDescriptor::new(); 4];
76-
#[cfg_attr(feature = "stm32h7xx-hal", link_section = ".sram1.eth2")]
77-
static mut RX_BUFFERS: [[u8; MTU + 2]; 4] = [[0u8; MTU + 2]; 4];
78-
7968
#[init]
8069
fn init(cx: init::Context) -> (Shared, Local, init::Monotonics) {
8170
defmt::info!("Pre-init");
8271
let core = cx.core;
8372
let p = cx.device;
8473

85-
let rx_ring =
86-
RxDescriptorRing::new(unsafe { &mut RX_DESCRIPTORS }, unsafe { &mut RX_BUFFERS });
87-
let tx_ring =
88-
TxDescriptorRing::new(unsafe { &mut TX_DESCRIPTORS }, unsafe { &mut TX_BUFFERS });
74+
let (tx_ring, rx_ring) = crate::common::setup_rings();
8975

9076
let (clocks, gpio, ethernet) = crate::common::setup_peripherals(p);
9177
let mono = Systick::new(core.SYST, clocks.hclk().raw());
@@ -192,7 +178,7 @@ mod app {
192178
buf[12..14].copy_from_slice(&ETH_TYPE);
193179
buf[14..22].copy_from_slice(&now.raw().to_be_bytes());
194180
})
195-
.ok();
181+
.unwrap();
196182
*tx_id = Some((tx_id_val, now));
197183
*tx_id_ctr += 1;
198184
*tx_id_ctr |= 0x8000_0000;
@@ -210,7 +196,7 @@ mod app {
210196
cx.shared.scheduled_time,
211197
)
212198
.lock(|dma, tx_id, ptp, _sched_time| {
213-
dma.interrupt_handler();
199+
let interrupt_summary = dma.interrupt_handler();
214200

215201
#[cfg(not(feature = "stm32f107"))]
216202
{
@@ -302,15 +288,17 @@ mod app {
302288
}
303289
}
304290

305-
if let Some((tx_id, sent_time)) = tx_id.take() {
306-
if let Ok(ts) = dma.get_timestamp_for_id(PacketId(tx_id)) {
307-
defmt::info!("TX timestamp: {}", ts);
308-
defmt::debug!(
291+
if interrupt_summary.is_tx {
292+
if let Some((tx_id, sent_time)) = tx_id.take() {
293+
if let Ok(ts) = dma.get_timestamp_for_id(PacketId(tx_id)) {
294+
defmt::info!("TX timestamp: {}", ts);
295+
defmt::debug!(
309296
"Diff between TX timestamp and the time that was put into the packet: {}",
310297
ts - sent_time
311298
);
312-
} else {
313-
defmt::warn!("Failed to retrieve TX timestamp");
299+
} else {
300+
defmt::warn!("Failed to retrieve TX timestamp");
301+
}
314302
}
315303
}
316304
});

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