Getting iverilog to output CUPL

[lampmerchant]

Hi all -

First of all, forgive my naïveté. :) I am, most of all, trying to get a handle on the complexity of what I'm looking for.

What I'd ultimately like to do is use iverilog as part of a toolchain that can be used to target the Microchip/Atmel ATF15xx series of CPLDs. Currently the toolchain suggested by Microchip is to use CUPL along with a fitter they provide, and while this works, CUPL is a lot less pleasant to code in than Verilog. If you aren't familiar with it, CUPL is to Verilog more or less what assembly language is to C. A CUPL source file consists primarily of equations which assign logic values either directly to nodes or to attributes of nodes - if a node is a DFF, for example, there would be equations for its D input, its clock input, and its asynchronous preset/reset.

Is the output of iverilog in any of its forms suitable for conversion to CUPL? What I propose could be a new target within the iverilog codebase or it could be an external converter for one of iverilog's existing targets such as VVP. The output doesn't have to be pretty, it just has to be something the CUPL compiler will compile.

I wouldn't ask any of the developers to do this for me, mind - I'm considering this as a project for myself, and what I seek is some expert opinions on what might be the best way to go about it, what code or documentation I'd do well to refer to, and/or whether it's feasible at all.

Thanks for taking a look at my question and for your work on iverilog!

[caryr]

I didn't look at CUPL much from a syntax standpoint, but as a minimum iverilog will need to support synthesizing the expressions you care about into gates. We do not actively maintain the synthesis portion of the code though it is tested so it does not degrade over time. It is likely that without enhancements you will need to code in a specific and reduced style since certain constructs cannot currently be synthesized. Once you have determined the synthesis is adequate or something you can extend to support what you need, look at the various back-ends and determine which generates code that most likely matches what you want.

I would initially use the vlog95 code generator to check the synthesis since it generates code that most closely matches the input. It could have constructs it doesn't convert properly, but as long as the synthesis is working you could extend the CUPS generator to support what is missing. I expect the easiest way to code the new generator is once you have some verilog code that tests the synthesis part of iverilog is working as expected, build the generator frame work and then output what you can generating an error message for what cannot be converted. You should start with simple logical expression and then work to more complex example. I assume all the timing is handled after the CUPL is generated so all you need to care about in the generation is the logical equivalence. Ask more specific questions and one of us will try to respond.

[lampmerchant]

Thanks for your reply!

I suppose I have a gap in understanding of what exactly "synthesis" is and is not. If synthesis is something that is done by the CUPL compiler and/or the Atmel fitter, I'm probably in better shape. From your reply, it sounds like iverilog has a synthesis component but it's not used for anything at the moment - but at the same time, I'm assuming iverilog has to be able to break down Verilog code into things like nodes and gates and flipflops in order to simulate code. If I'm correct, then the challenge is just to get that into a form understood by the CUPL compiler. Is this correct, or am I off in the weeds?

[caryr]

In general iverilog executes SystemVerilog, but this is often more than just gates and flip-flops. Synthesis will covert behavioral RTL into actual logical primitive. iverilog has some support for synthesis, but its primary function and implementation focus is to execute all of SystemVerilog not just the synthesizable subset and converting this to primitives. It does not by default convert RTL for flops/latches into flop/latch primitives. The same for case statements, etc. To get what you want you need to use the synthesis inside iverilog to get only gate primitives for the design part which can then be converted into CUPL for processing by the other tools.

This is why you need to determine what subset of the synthesizable RTL you can live with and then verify that iverilog supports it properly. If it is deficient then it would need to be extended before you can have a properly functioning converter. The gate primitives to CUPL generation should be relatively simple to implement.

This is why I suggested verifying that iverilog support the synthesis you need to make this work.

[lampmerchant]

Ok, I'll do that. Thanks for the information!