Coverage analysis

[Srimathy-R]

Is it possible to generate coverage report in icarus verilog where my design file is either in verilog or systerm verilog and testbench file is in cocotb(python testbench)?

[martinwhitaker]

There is no support for coverage analysis in Icarus Verilog.

Moving to the Q&A section under Discussions.

[caryr]

I have used the coverage tool covered in the past, but it has not been maintained in a long time so I do not know if it is still functional.