Reset the inline flag for accessors in traits at Mixin.

sjrd · sjrd · commit 3f999152a3ff · 2020-07-22T10:23:32.000+02:00
This might not be the best way to fix t4753.scala, but this is the
last run test and I'll take anything that makes the tests pass at
this point.
diff --git a/compiler/src/dotty/tools/dotc/transform/Mixin.scala b/compiler/src/dotty/tools/dotc/transform/Mixin.scala
@@ -131,7 +131,7 @@ class Mixin extends MiniPhase with SymTransformer { thisPhase =>
     if (sym.is(Accessor, butNot = Deferred) && sym.owner.is(Trait)) {
       val sym1 =
         if (sym.is(Lazy)) sym
-        else sym.copySymDenotation(initFlags = sym.flags &~ ParamAccessor | Deferred)
+        else sym.copySymDenotation(initFlags = sym.flags &~ (ParamAccessor | Inline) | Deferred)
       sym1.ensureNotPrivate
     }
     else if sym.isAllOf(ModuleClass | Private) && sym.owner.is(Trait) then

Original file line number	Diff line number	Diff line change
`@@ -131,7 +131,7 @@ class Mixin extends MiniPhase with SymTransformer { thisPhase =>`
`131`	`131`	`if (sym.is(Accessor, butNot = Deferred) && sym.owner.is(Trait)) {`
`132`	`132`	`val sym1 =`
`133`	`133`	`if (sym.is(Lazy)) sym`
`134`		`- else sym.copySymDenotation(initFlags = sym.flags &~ ParamAccessor \| Deferred)`
	`134`	`+ else sym.copySymDenotation(initFlags = sym.flags &~ (ParamAccessor \| Inline) \| Deferred)`
`135`	`135`	`sym1.ensureNotPrivate`
`136`	`136`	`}`
`137`	`137`	`else if sym.isAllOf(ModuleClass \| Private) && sym.owner.is(Trait) then`