hal: GPIO support (register level)

Signed-off-by: zhujunxing <zjx1319@hust.edu.cn>

Author: jakezhu9

Cargo.lock

@@ -11,3 +11,7 @@ repository.workspace = true
 [dependencies]
 base-address = "0.0.0"
 uart16550 = "0.0.1"
+volatile-register = "0.2.1"
+
+[dev-dependencies]
+memoffset = "0.9.0"

sophgo-hal/Cargo.toml

@@ -0,0 +1,84 @@
+//! General Purpose Input/Output.
+
+use volatile_register::{RO, RW, WO};
+
+/// GPIO registers.
+#[repr(C)]
+pub struct RegisterBlock {
+    /// Port A data register.
+    pub data: RW<u32>,
+    /// Port A data direction register.
+    pub direction: RW<Direction>,
+    _reserved0: [u8; 0x28],
+    /// Interrupt enable register.
+    pub interrupt_enable: RW<u32>,
+    /// Interrupt mask register.
+    pub interrupt_mask: RW<u32>,
+    /// Interrupt level register.
+    pub interrupt_level: RW<u32>,
+    /// Interrupt polarity register.
+    pub interrupt_polarity: RW<u32>,
+    /// Interrupt status register.
+    pub interrupt_status: RO<u32>,
+    /// Raw interrupt status register.
+    pub raw_interrupt_status: RO<u32>,
+    /// Debounce enable register.
+    pub debounce: RW<u32>,
+    /// Port A clear interrupt register.
+    pub interrupt_clear: WO<u32>,
+    /// Port A external port register.
+    pub external_port: RW<u32>,
+    _reserved1: [u8; 0xC],
+    /// Level-sensitive synchronization enable register.
+    pub sync_level: RW<u32>,
+}
+
+/// GPIO direction.
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
+#[repr(transparent)]
+pub struct Direction(u32);
+
+impl Direction {
+    /// Set GPIO direction to input.
+    #[inline]
+    pub fn set_input(self, n: u8) -> Self {
+        Self(self.0 & !(1 << n))
+    }
+    /// Set GPIO direction to output.
+    #[inline]
+    pub fn set_output(self, n: u8) -> Self {
+        Self(self.0 | (1 << n))
+    }
+    /// Check if GPIO direction is input.
+    #[inline]
+    pub fn is_input(self, n: u8) -> bool {
+        self.0 & (1 << n) == 0
+    }
+    /// Check if GPIO direction is output.
+    #[inline]
+    pub fn is_output(self, n: u8) -> bool {
+        self.0 & (1 << n) != 0
+    }
+}
+
+#[cfg(test)]
+mod tests {
+    use super::RegisterBlock;
+    use memoffset::offset_of;
+
+    #[test]
+    fn struct_register_block_offset() {
+        assert_eq!(offset_of!(RegisterBlock, data), 0x00);
+        assert_eq!(offset_of!(RegisterBlock, direction), 0x04);
+        assert_eq!(offset_of!(RegisterBlock, interrupt_enable), 0x30);
+        assert_eq!(offset_of!(RegisterBlock, interrupt_mask), 0x34);
+        assert_eq!(offset_of!(RegisterBlock, interrupt_level), 0x38);
+        assert_eq!(offset_of!(RegisterBlock, interrupt_polarity), 0x3C);
+        assert_eq!(offset_of!(RegisterBlock, interrupt_status), 0x40);
+        assert_eq!(offset_of!(RegisterBlock, raw_interrupt_status), 0x44);
+        assert_eq!(offset_of!(RegisterBlock, debounce), 0x48);
+        assert_eq!(offset_of!(RegisterBlock, interrupt_clear), 0x4C);
+        assert_eq!(offset_of!(RegisterBlock, external_port), 0x50);
+        assert_eq!(offset_of!(RegisterBlock, sync_level), 0x60);
+    }
+}

sophgo-hal/src/gpio.rs

@@ -1,5 +1,7 @@
 #![no_std]
 
+pub mod gpio;
+
 use core::ops;
 
 use base_address::BaseAddress;
@@ -17,3 +19,17 @@ impl<A: BaseAddress> ops::Deref for UART<A> {
         unsafe { &*(self.base.ptr() as *const _) }
     }
 }
+
+/// General Purpose Input/Output.
+pub struct GPIO<A: BaseAddress> {
+    base: A,
+}
+
+impl<A: BaseAddress> ops::Deref for GPIO<A> {
+    type Target = gpio::RegisterBlock;
+
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*(self.base.ptr() as *const _) }
+    }
+}

sophgo-hal/src/lib.rs

@@ -7,8 +7,51 @@ use base_address::Static;
 
 /// Peripherals available on ROM start.
 pub struct Peripherals {
+    // TODO pub pin_mux: sophgo_hal::PinMux<Static<0x03001000>>,
+    /// General Purpose Input/Output 0.
+    pub gpio0: sophgo_hal::GPIO<Static<0x03020000>>,
+    /// General Purpose Input/Output 1.
+    pub gpio1: sophgo_hal::GPIO<Static<0x03021000>>,
+    /// General Purpose Input/Output 2.
+    pub gpio2: sophgo_hal::GPIO<Static<0x03022000>>,
+    /// General Purpose Input/Output 3.
+    pub gpio3: sophgo_hal::GPIO<Static<0x03023000>>,
+
+    // TODO pub pwm0: sophgo_hal::PWM<Static<0x03060000>>,
+    // TODO pub pwm1: sophgo_hal::PWM<Static<0x03061000>>,
+    // TODO pub pwm2: sophgo_hal::PWM<Static<0x03062000>>,
+    // TODO pub pwm3: sophgo_hal::PWM<Static<0x03063000>>,
+    // TODO pub timer: sophgo_hal::Timer<Static<0x030A0000>>,
+    // TODO pub i2c0: sophgo_hal::I2C<Static<0x04000000>>,
+    // TODO pub i2c1: sophgo_hal::I2C<Static<0x04010000>>,
+    // TODO pub i2c2: sophgo_hal::I2C<Static<0x04020000>>,
+    // TODO pub i2c3: sophgo_hal::I2C<Static<0x04030000>>,
+    // TODO pub i2c4: sophgo_hal::I2C<Static<0x04040000>>,
+    // TODO pub spi_nand: sophgo_hal::SPINand<Static<0x04060000>>,
+    // TODO pub i2s0: sophgo_hal::I2S<Static<0x04100000>>,
+    // TODO pub i2s1: sophgo_hal::I2S<Static<0x04110000>>,
+    // TODO pub i2s2: sophgo_hal::I2S<Static<0x04120000>>,
+    // TODO pub i2s3: sophgo_hal::I2S<Static<0x04130000>>,
     /// Universal Asynchronous Receiver/Transmitter 0.
     pub uart0: sophgo_hal::UART<Static<0x04140000>>,
+    /// Universal Asynchronous Receiver/Transmitter 1.
+    pub uart1: sophgo_hal::UART<Static<0x04150000>>,
+    /// Universal Asynchronous Receiver/Transmitter 2.
+    pub uart2: sophgo_hal::UART<Static<0x04160000>>,
+    /// Universal Asynchronous Receiver/Transmitter 3.
+    pub uart3: sophgo_hal::UART<Static<0x04170000>>,
+
+    // TODO spi0: sophgo_hal::SPI<Static<0x04180000>>,
+    // TODO spi1: sophgo_hal::SPI<Static<0x04190000>>,
+    // TODO spi2: sophgo_hal::SPI<Static<0x041A0000>>,
+    // TODO spi3: sophgo_hal::SPI<Static<0x041B0000>>,
+    /// Universal Asynchronous Receiver/Transmitter 4.
+    pub uart4: sophgo_hal::UART<Static<0x041C0000>>,
+    // TODO sd0: sophgo_hal::SD<Static<0x04310000>>,
+    // TODO sd1: sophgo_hal::SD<Static<0x04320000>>,
+    // TODO usb: sophgo_hal::USB<Static<0x04340000>>,
+    // TODO documents
+    pub rtc_gpio: sophgo_hal::GPIO<Static<0x05021000>>,
 }
 
 #[cfg(target_arch = "riscv64")]