feat(sbi): 处理 mtimer 和非法指令

Author: YdrMaster

rustsbi-qemu/src/execute/mod.rs

@@ -9,9 +9,31 @@ struct Context {
     mepc: usize,
 }
 
+impl Context {
+    #[inline]
+    fn a(&self, n: usize) -> usize {
+        self.x[n + 9]
+    }
+
+    #[inline]
+    fn a_mut(&mut self, n: usize) -> &mut usize {
+        &mut self.x[n + 9]
+    }
+
+    #[inline]
+    fn x(&self, n: usize) -> usize {
+        self.x[n - 1]
+    }
+
+    #[inline]
+    fn x_mut(&mut self, n: usize) -> &mut usize {
+        &mut self.x[n - 1]
+    }
+}
+
 pub(crate) fn execute_supervisor(supervisor: Supervisor) {
     use core::arch::asm;
-    use riscv::register::{medeleg, mie, mip, mstatus};
+    use riscv::register::{medeleg, mie, mstatus};
 
     unsafe {
         mstatus::set_mpp(mstatus::MPP::Supervisor);
@@ -67,11 +89,51 @@ pub(crate) fn execute_supervisor(supervisor: Supervisor) {
                 ctx.mepc = ctx.mepc.wrapping_add(4);
             }
             T::Interrupt(I::MachineTimer) => unsafe {
+                use riscv::register::mip;
                 mip::clear_mtimer();
                 mip::set_stimer();
             },
             T::Exception(E::IllegalInstruction) => {
-                println!("TODO emulate or forward illegal instruction");
+                use riscv::register::mtval;
+
+                const OPCODE_MASK: usize = (1 << 7) - 1;
+                const REG_MASK: usize = (1 << 5) - 1;
+                const OPCODE_CSR: usize = 0b1110011;
+                const CSR_TIME: usize = 0xc01;
+                let instruction = mtval::read();
+                // 标准 20191213 的表 24.3 列出了一些特殊的 CSR，SBI 软件负责将它们模拟出来
+                if let OPCODE_CSR = instruction & OPCODE_MASK {
+                    if instruction >> 20 == CSR_TIME {
+                        match (instruction >> 7) & REG_MASK {
+                            0 => {}
+                            rd => *ctx.x_mut(rd) = crate::clint::get().get_mtime() as _,
+                        }
+                        continue;
+                    }
+                }
+                // 如果不是可修正的指令，且不是 M 态本身发出的，转交给 S 态处理
+                // mpp != machine
+                if (ctx.mstatus >> 11) & 0b11 != 0b11 {
+                    use riscv::register::{
+                        scause::{self, Exception, Trap},
+                        sepc, stval, stvec,
+                    };
+                    unsafe {
+                        scause::set(Trap::Exception(Exception::IllegalInstruction));
+                        stval::write(instruction);
+                        sepc::write(ctx.mepc);
+                        mstatus::set_mpp(mstatus::MPP::Supervisor);
+                        mstatus::set_spp(mstatus::SPP::Supervisor);
+                        if mstatus::read().sie() {
+                            mstatus::set_spie()
+                        }
+                        mstatus::clear_sie();
+                        core::arch::asm!("csrr {}, mstatus", out(reg) ctx.mstatus);
+                        ctx.mepc = stvec::read().address();
+                    }
+                    continue;
+                }
+                println!("{:?}", E::IllegalInstruction);
                 break;
             }
             t => {
@@ -85,18 +147,6 @@ pub(crate) fn execute_supervisor(supervisor: Supervisor) {
     }
 }
 
-impl Context {
-    #[inline]
-    fn a(&self, n: usize) -> usize {
-        self.x[9 + n]
-    }
-
-    #[inline]
-    fn a_mut(&mut self, n: usize) -> &mut usize {
-        &mut self.x[9 + n]
-    }
-}
-
 /// M 态转到 S 态。
 ///
 /// # Safety

test-kernel/src/main.rs

@@ -109,8 +109,8 @@ extern "C" fn primary_rust_main(hartid: usize, dtb_pa: usize) -> ! {
     test::base_extension();
     test::sbi_ins_emulation();
 
-    // unsafe { stvec::write(start_trap as usize, TrapMode::Direct) };
-    // test::trap_delegate(hartid);
+    unsafe { stvec::write(start_trap as usize, TrapMode::Direct) };
+    test::trap_delegate(hartid);
 
     println!();
     STARTED.fetch_add(1, Ordering::SeqCst);