build: update deps

- Updating dtb-walker v0.1.3 -> v0.2.0-alpha.3
- Updating hashbrown v0.12.2 -> v0.12.3
- Updating os_str_bytes v6.1.0 -> v6.2.0
- Updating rustversion v1.0.7 -> v1.0.8
- Updating spin v0.9.3 -> v0.9.4
- Updating unicode-ident v1.0.1 -> v1.0.2
- Updating x86_64 v0.14.9 -> v0.14.10

Signed-off-by: YdrMaster <ydrml@hotmail.com>

Author: YdrMaster

Cargo.lock

@@ -13,5 +13,5 @@ riscv = "0.8"
 spin = "0.9"
 r0 = "1"
 uart_16550 = "0.2"
-dtb-walker = "0.1.3"
+dtb-walker = "=0.2.0-alpha.3"
 qemu-exit = "3.0"

rustsbi-qemu/Cargo.toml

@@ -27,13 +27,13 @@ impl<const N: usize> Display for StringInline<N> {
 
 /// 解析设备树。
 pub(crate) fn parse(opaque: usize) -> BoardInfo {
-    use dtb_walker::{Dtb, DtbObj, HeaderError as E, Property, WalkOperation::*};
-    const CPUS: &[u8] = b"cpus";
-    const MEMORY: &[u8] = b"memory";
-    const SOC: &[u8] = b"soc";
-    const UART: &[u8] = b"uart";
-    const TEST: &[u8] = b"test";
-    const CLINT: &[u8] = b"clint";
+    use dtb_walker::{Dtb, DtbObj, HeaderError as E, Property, Str, WalkOperation::*};
+    const CPUS: &str = "cpus";
+    const MEMORY: &str = "memory";
+    const SOC: &str = "soc";
+    const UART: &str = "uart";
+    const TEST: &str = "test";
+    const CLINT: &str = "clint";
 
     let mut ans = BoardInfo {
         dtb: opaque..opaque,
@@ -51,35 +51,35 @@ pub(crate) fn parse(opaque: usize) -> BoardInfo {
     }
     .unwrap();
     ans.dtb.end += dtb.total_size();
-    dtb.walk(|path, obj| match obj {
+    dtb.walk(|ctx, obj| match obj {
         DtbObj::SubNode { name } => {
-            let current = path.last();
-            if current.is_empty() {
-                if name == CPUS || name == SOC || name.starts_with(MEMORY) {
+            let current = ctx.name();
+            if ctx.is_root() {
+                if name == Str::from(CPUS) || name == Str::from(SOC) || name.starts_with(MEMORY) {
                     StepInto
                 } else {
                     StepOver
                 }
-            } else if current == SOC {
+            } else if current == Str::from(SOC) {
                 if name.starts_with(UART) || name.starts_with(TEST) || name.starts_with(CLINT) {
                     StepInto
                 } else {
                     StepOver
                 }
             } else {
-                if current == CPUS && name.starts_with(b"cpu@") {
+                if current == Str::from(CPUS) && name.starts_with("cpu@") {
                     ans.smp += 1;
                 }
                 StepOver
             }
         }
-        DtbObj::Property(Property::Model(model)) if path.last().is_empty() => {
+        DtbObj::Property(Property::Model(model)) if ctx.is_root() => {
             ans.model.0 = model.as_bytes().len();
             ans.model.1[..ans.model.0].copy_from_slice(model.as_bytes());
             StepOver
         }
         DtbObj::Property(Property::Reg(mut reg)) => {
-            let node = path.last();
+            let node = ctx.name();
             if node.starts_with(UART) {
                 ans.uart = reg.next().unwrap();
                 StepOut

rustsbi-qemu/src/device_tree.rs

@@ -13,4 +13,4 @@ riscv = "0.8"
 spin = "0.9"
 r0 = "1"
 uart_16550 = "0.2"
-dtb-walker = "0.1.3"
+dtb-walker = "=0.2.0-alpha.3"

test-kernel/Cargo.toml

@@ -260,7 +260,7 @@ struct BoardInfo {
 }
 
 fn parse_smp(dtb_pa: usize) -> BoardInfo {
-    use dtb_walker::{Dtb, DtbObj, HeaderError as E, Property, WalkOperation::*};
+    use dtb_walker::{Dtb, DtbObj, HeaderError as E, Property, Str, WalkOperation::*};
 
     let mut ans = BoardInfo { smp: 0, uart: 0 };
     unsafe {
@@ -269,21 +269,21 @@ fn parse_smp(dtb_pa: usize) -> BoardInfo {
         })
     }
     .unwrap()
-    .walk(|path, obj| match obj {
+    .walk(|ctx, obj| match obj {
         DtbObj::SubNode { name } => {
-            if path.last().is_empty() && (name == b"cpus" || name == b"soc") {
+            if ctx.is_root() && (name == Str::from("cpus") || name == Str::from("soc")) {
                 StepInto
-            } else if path.last() == b"cpus" && name.starts_with(b"cpu@") {
+            } else if ctx.name() == Str::from("cpus") && name.starts_with("cpu@") {
                 ans.smp += 1;
                 StepOver
-            } else if path.last() == b"soc" && name.starts_with(b"uart") {
+            } else if ctx.name() == Str::from("soc") && name.starts_with("uart") {
                 StepInto
             } else {
                 StepOver
             }
         }
         DtbObj::Property(Property::Reg(mut reg)) => {
-            if path.last().starts_with(b"uart") {
+            if ctx.name().starts_with("uart") {
                 ans.uart = reg.next().unwrap().start;
             }
             StepOut