Merge branch 'main' into multicore

Author: luojia65

.vscode/settings.json

@@ -0,0 +1,10 @@
+{   
+    // Prevent "can't find crate for `test`" error on no_std
+    // Ref: https://github.com/rust-lang/vscode-rust/issues/729
+    // For vscode-rust plugin users:
+    "rust.target": "riscv64imac-unknown-none-elf",
+    "rust.all_targets": false,
+    // For Rust Analyzer plugin users:
+    "rust-analyzer.cargo.target": "riscv64imac-unknown-none-elf",
+    "rust-analyzer.checkOnSave.allTargets": false
+}

Cargo.lock

@@ -9,28 +9,31 @@ cargo qemu
 When running `cargo qemu`, the test kernel will build and run. Expected output should be:
 
 ```
+    Finished dev [unoptimized + debuginfo] target(s) in 0.03s
+     Running `target\debug\xtask.exe qemu`
 xtask: mode: Debug
-   Compiling rustsbi-qemu v0.1.0 (D:\RustProjects\rustsbi-qemu\rustsbi-qemu)
-    Finished dev [unoptimized + debuginfo] target(s) in 1.09s
-    Finished dev [unoptimized + debuginfo] target(s) in 0.23s
-[rustsbi] RustSBI version 0.2.0-alpha.3
+   Compiling rustsbi-qemu v0.0.2 (D:\RustSBI\rustsbi-qemu\rustsbi-qemu)
+    Finished dev [unoptimized + debuginfo] target(s) in 0.44s
+    Finished dev [unoptimized + debuginfo] target(s) in 0.04s
+[rustsbi] RustSBI version 0.2.0-alpha.7
 .______       __    __      _______.___________.  _______..______   __
 |   _  \     |  |  |  |    /       |           | /       ||   _  \ |  |
 |  |_)  |    |  |  |  |   |   (----`---|  |----`|   (----`|  |_)  ||  |
 |      /     |  |  |  |    \   \       |  |      \   \    |   _  < |  |
 |  |\  \----.|  `--'  |.----)   |      |  |  .----)   |   |  |_)  ||  |
 | _| `._____| \______/ |_______/       |__|  |_______/    |______/ |__|
 
-[rustsbi] Implementation: RustSBI-QEMU Version 0.0.1
-[rustsbi-dtb] Hart count: cluster0 with 1 cores
+[rustsbi] Implementation: RustSBI-QEMU Version 0.0.2
+[rustsbi-dtb] Hart count: cluster0 with 8 cores
 [rustsbi] misa: RV64ACDFIMSU
 [rustsbi] mideleg: ssoft, stimer, sext (0x222)
 [rustsbi] medeleg: ima, ia, bkpt, la, sa, uecall, ipage, lpage, spage (0xb1ab)
-[rustsbi] pmp0: 0x80000000 ..= 0x800fffff (rwx)
-[rustsbi] pmp1: 0x80200000 ..= 0x802fffff (rwx)
-[rustsbi] pmp2: 0x0 ..= 0xfffffffffffffffc (---)
+[rustsbi] pmp0: 0x10000000 ..= 0x10001fff (rwx)
+[rustsbi] pmp1: 0x80000000 ..= 0x8fffffff (rwx)
+[rustsbi] pmp2: 0x0 ..= 0xffffffffffffff (---)
+D:\Applications\Scoop\apps\qemu\current\qemu-system-riscv64.exe: clint: invalid write: 00000020
 [rustsbi] enter supervisor 0x80200000
-<< Test-kernel: Hart id = 0, DTB physical address = 0x87e00000
+<< Test-kernel: Hart id = 0, DTB physical address = 0x87000000
 >> Test-kernel: Testing base extension
 << Test-kernel: Base extension version: 1
 << Test-kernel: SBI specification version: 2
@@ -40,11 +43,25 @@ xtask: mode: Debug
 << Test-kernel: Device marchid: 0
 << Test-kernel: Device mimpid: 0
 >> Test-kernel: Testing SBI instruction emulation
-<< Test-kernel: Current time: 31918a
+<< Test-kernel: Current time: d1540
+<< Test-kernel: Time after operation: d407b
 >> Test-kernel: Trigger illegal exception
 << Test-kernel: Value of scause: Exception(IllegalInstruction)
 << Test-kernel: Illegal exception delegate success
-<< Test-kernel: SBI test SUCCESS, shutdown
+>> Stop hart 3, return value 0
+>> Hart 0 state return value: 0
+>> Hart 1 state return value: 4
+>> Hart 2 state return value: 4
+>> Hart 3 state return value: 1
+<< Test-kernel: test for hart 0 success, wake another hart
+>> Wake hart 1, sbi return value 0
+>> Start test for hart 1, retentive suspend return value 0
+>> Wake hart 2, sbi return value 0
+<< The parameter passed to hart 2 resume is: 0x4567890a
+>> Start hart 3 with parameter 0x12345678
+>> SBI return value: 0
+<< The parameter passed to hart 3 start is: 0x12345678
+<< Test-kernel: All hart SBI test SUCCESS, shutdown
 ```
 
 ## Run test kernel

README.md

@@ -6,7 +6,7 @@ edition = "2018"
 # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
 
 [dependencies]
-rustsbi = { version = "0.2.0-alpha.6" }
+rustsbi = { version = "0.2.0-alpha.7" }
 buddy_system_allocator = "0.8"
 lazy_static = { version = "1", features = ["spin_no_std"] }
 spin = "0.9"

rustsbi-qemu/Cargo.toml

@@ -19,9 +19,22 @@ pub fn execute_supervisor(supervisor_mepc: usize, a0: usize, a1: usize, hsm: Qem
                 let ctx = rt.context_mut();
                 let param = [ctx.a0, ctx.a1, ctx.a2, ctx.a3, ctx.a4, ctx.a5];
                 let ans = rustsbi::ecall(ctx.a7, ctx.a6, param);
-                ctx.a0 = ans.error;
-                ctx.a1 = ans.value;
-                ctx.mepc = ctx.mepc.wrapping_add(4);
+                if ans.error == 0x233 { // hart non-retentive resume
+                    if let Some(HsmCommand::Start(start_paddr, opaque)) = hsm.last_command() {
+                        unsafe {
+                            riscv::register::satp::write(0);
+                            riscv::register::sstatus::clear_sie();
+                        }
+                        hsm.record_current_start_finished();
+                        ctx.mstatus = riscv::register::mstatus::read(); // get from modified sstatus
+                        ctx.a0 = opaque;
+                        ctx.mepc = start_paddr;
+                    }
+                } else {
+                    ctx.a0 = ans.error;
+                    ctx.a1 = ans.value;
+                    ctx.mepc = ctx.mepc.wrapping_add(4);
+                }
             }
             GeneratorState::Yielded(MachineTrap::IllegalInstruction()) => {
                 let ctx = rt.context_mut();
@@ -45,38 +58,24 @@ pub fn execute_supervisor(supervisor_mepc: usize, a0: usize, a1: usize, hsm: Qem
                 mie::clear_mtimer();
             },
             GeneratorState::Yielded(MachineTrap::MachineSoft()) => match hsm.last_command() {
-                Some(HsmCommand::Start(start_addr, opaque)) => {
-                    unsafe {
-                        riscv::register::satp::write(0);
-                        riscv::register::sstatus::clear_sie();
-                    }
-                    hsm.record_current_start_finished();
-                    match () {
-                        #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
-                        () => unsafe {
-                            asm!(
-                                "csrr   a0, mhartid",
-                                "jr     {start_addr}",
-                                start_addr = in(reg) start_addr,
-                                in("a1") opaque,
-                                options(noreturn)
-                            )
-                        },
-                        #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
-                        () => {
-                            drop((start_addr, opaque));
-                            unimplemented!("not RISC-V instruction set architecture")
-                        }
-                    };
-                }
+                Some(HsmCommand::Start(_start_paddr, _opaque)) => panic!("rustsbi-qemu: illegal state"),
                 Some(HsmCommand::Stop) => {
                     // no hart stop command in qemu, record stop state and pause
                     hsm.record_current_stop_finished();
                     pause();
-                }
-                None => panic!(
-                    "rustsbi-qemu: machine soft interrupt with no hart state monitor command"
-                ),
+                    if let Some(HsmCommand::Start(start_paddr, opaque)) = hsm.last_command() {
+                        unsafe {
+                            riscv::register::satp::write(0);
+                            riscv::register::sstatus::clear_sie();
+                        }
+                        hsm.record_current_start_finished();
+                        let ctx = rt.context_mut();
+                        ctx.mstatus = riscv::register::mstatus::read(); // get from modified sstatus
+                        ctx.a0 = opaque;
+                        ctx.mepc = start_paddr;
+                    }
+                },
+                None => panic!("rustsbi-qemu: machine soft interrupt with no hart state monitor command"),
             },
             GeneratorState::Complete(()) => {
                 use rustsbi::Reset;

rustsbi-qemu/src/execute.rs

@@ -1,7 +1,7 @@
 #![no_std]
 #![no_main]
 #![feature(naked_functions)]
-#![feature(asm)]
+#![feature(asm, asm_sym, asm_const)]
 #![feature(generator_trait)]
 #![feature(default_alloc_error_handler)]
 
@@ -122,7 +122,7 @@ fn init_test_device() {
     init_reset(test_device::Reset);
 }
 
-// 委托终端；把S的中断全部委托给S层
+// 委托中断；把S的中断全部委托给S层
 fn delegate_interrupt_exception() {
     use riscv::register::{medeleg, mideleg, mie};
     unsafe {
@@ -149,6 +149,8 @@ fn delegate_interrupt_exception() {
 
 fn set_pmp() {
     // todo: 根据QEMU的loader device等等，设置这里的权限配置
+    // read fdt tree value, parse, and calculate proper pmp configuration for this device tree (issue #7)
+    // integrate with `count_harts`
     unsafe {
         asm!(
             "li     {tmp}, ((0x08 << 16) | (0x1F << 8) | (0x1F << 0) )", // 0 = NAPOT,ARWX; 1 = NAPOT,ARWX; 2 = TOR,A;