feat(sbi): 只向状态是可以接受核间中断的核发中断

YdrMaster · YdrMaster · commit 2b3de3da1e82 · 2022-05-24T16:37:39.000+08:00
diff --git a/rustsbi-qemu/src/clint.rs b/rustsbi-qemu/src/clint.rs
@@ -9,13 +9,12 @@ use spin::Once;
 
 pub(crate) struct Clint {
     base: usize,
-    smp: usize,
 }
 
 static CLINT: Once<Clint> = Once::new();
 
-pub(crate) fn init(base: usize, smp: usize) {
-    CLINT.call_once(|| Clint { base, smp });
+pub(crate) fn init(base: usize) {
+    CLINT.call_once(|| Clint { base });
 }
 
 pub(crate) fn get() -> &'static Clint {
@@ -42,9 +41,9 @@ impl Clint {
 impl Ipi for &'static Clint {
     #[inline]
     fn send_ipi_many(&self, hart_mask: HartMask) -> SbiRet {
-        // println!("[rustsbi] send ipi many, {:?}", hart_mask);
-        for i in 0..self.smp {
-            if hart_mask.has_bit(i) {
+        let hsm = crate::HSM.wait();
+        for i in 0..crate::NUM_HART_MAX {
+            if hart_mask.has_bit(i) && hsm.is_ipi_allowed(i) {
                 self.send_soft(i);
             }
         }
diff --git a/rustsbi-qemu/src/execute/context.rs b/rustsbi-qemu/src/execute/context.rs
@@ -40,8 +40,8 @@ impl Context {
     //     self.x[n - 1]
     // }
 
-    #[inline]
-    pub fn x_mut(&mut self, n: usize) -> &mut usize {
-        &mut self.x[n - 1]
-    }
+    // #[inline]
+    // pub fn x_mut(&mut self, n: usize) -> &mut usize {
+    //     &mut self.x[n - 1]
+    // }
 }
diff --git a/rustsbi-qemu/src/execute/mod.rs b/rustsbi-qemu/src/execute/mod.rs
@@ -33,29 +33,24 @@ pub(crate) fn execute_supervisor(supervisor: Supervisor) {
 
     loop {
         use crate::qemu_hsm::{EID_HSM, FID_HART_STOP, FID_HART_SUSPEND, SUSPEND_NON_RETENTIVE};
-        use riscv::register::mcause::{self, Exception as E, Interrupt as I, Trap as T};
+        use riscv::register::{
+            mcause::{self, Exception as E, Interrupt as I, Trap as T},
+            mip,
+        };
 
         unsafe { m_to_s(&mut ctx) };
 
         match mcause::read().cause() {
             T::Interrupt(I::MachineTimer) => unsafe {
-                use riscv::register::mip;
+                mie::clear_mtimer();
                 mip::clear_mtimer();
                 mip::set_stimer();
             },
             T::Interrupt(I::MachineSoft) => {
-                use riscv::register::{mip, scause};
-
                 crate::clint::get().clear_soft(hart_id());
-                unsafe { mip::clear_msoft() };
-                if transfer_trap::should_transfer_trap(&ctx) {
-                    transfer_trap::do_transfer_trap(
-                        &mut ctx,
-                        scause::Trap::Interrupt(scause::Interrupt::SupervisorSoft),
-                    );
-                } else {
-                    println!("{:?}", I::MachineSoft);
-                    break;
+                unsafe {
+                    mip::clear_msoft();
+                    mip::set_ssoft();
                 }
             }
             T::Exception(E::SupervisorEnvCall) => {
@@ -74,23 +69,24 @@ pub(crate) fn execute_supervisor(supervisor: Supervisor) {
                 ctx.mepc = ctx.mepc.wrapping_add(4);
             }
             T::Exception(E::IllegalInstruction) => {
-                use riscv::register::{mtval, scause};
+                use riscv::register::scause;
 
-                const OPCODE_MASK: usize = (1 << 7) - 1;
-                const REG_MASK: usize = (1 << 5) - 1;
-                const OPCODE_CSR: usize = 0b1110011;
-                const CSR_TIME: usize = 0xc01;
-                let instruction = mtval::read();
+                // const OPCODE_MASK: usize = (1 << 7) - 1;
+                // const REG_MASK: usize = (1 << 5) - 1;
+                // const OPCODE_CSR: usize = 0b1110011;
+                // const CSR_TIME: usize = 0xc01;
+                // let instruction = mtval::read();
                 // 标准 20191213 的表 24.3 列出了一些特殊的 CSR，SBI 软件负责将它们模拟出来
-                if let OPCODE_CSR = instruction & OPCODE_MASK {
-                    if instruction >> 20 == CSR_TIME {
-                        match (instruction >> 7) & REG_MASK {
-                            0 => {}
-                            rd => *ctx.x_mut(rd) = crate::clint::get().get_mtime() as _,
-                        }
-                        continue;
-                    }
-                }
+                // Qemu 似乎不需要模拟 time
+                // if let OPCODE_CSR = instruction & OPCODE_MASK {
+                //     if instruction >> 20 == CSR_TIME {
+                //         match (instruction >> 7) & REG_MASK {
+                //             0 => {}
+                //             rd => *ctx.x_mut(rd) = crate::clint::get().get_mtime() as _,
+                //         }
+                //         continue;
+                //     }
+                // }
                 // 如果不是可修正的指令，且不是 M 态本身发出的，转交给 S 态处理
                 // mpp != machine
                 if transfer_trap::should_transfer_trap(&ctx) {
diff --git a/rustsbi-qemu/src/main.rs b/rustsbi-qemu/src/main.rs
@@ -105,20 +105,31 @@ extern "C" fn early_trap() -> ! {
     }
 }
 
+use core::sync::atomic::{
+    AtomicBool, AtomicUsize,
+    Ordering::{AcqRel, Acquire},
+};
 use spin::Once;
 
 #[link_section = ".bss.uninit"]
 static HSM: Once<qemu_hsm::QemuHsm> = Once::new();
 
+#[link_section = ".bss.uninit"]
+static SMP: AtomicUsize = AtomicUsize::new(0);
+
 /// rust 入口。
 extern "C" fn rust_main(_hartid: usize, opaque: usize) {
-    use core::sync::atomic::{AtomicBool, Ordering::AcqRel};
-
     unsafe { set_mtcev(early_trap as _) };
 
     #[link_section = ".bss.uninit"]
     static GENESIS: AtomicBool = AtomicBool::new(false);
 
+    let mut smp = SMP.load(Acquire);
+    let mask = 1 << hart_id();
+    while let Err(val) = SMP.compare_exchange(smp, smp | mask, AcqRel, Acquire) {
+        smp = val;
+    }
+
     // 全局初始化过程
     if !GENESIS.swap(true, AcqRel) {
         // 清零 bss 段
@@ -128,7 +139,7 @@ extern "C" fn rust_main(_hartid: usize, opaque: usize) {
         // 解析设备树，需要堆来保存结果里的字符串等
         let board_info = device_tree::parse(opaque);
         // 初始化外设
-        clint::init(board_info.clint.start, board_info.smp);
+        clint::init(board_info.clint.start);
         test_device::init(board_info.test.start);
         let uart = unsafe { ns16550a::Ns16550a::new(board_info.uart.start) };
         let hsm = HSM.call_once(|| qemu_hsm::QemuHsm::new(clint::get(), board_info.smp, opaque));
diff --git a/rustsbi-qemu/src/qemu_hsm.rs b/rustsbi-qemu/src/qemu_hsm.rs
@@ -136,6 +136,17 @@ impl QemuHsm {
         use core::sync::atomic::Ordering::Release;
         self.state[hart_id()].store(STARTED, Release);
     }
+
+    /// 如果一个核可以接受 ipi，返回 `true`。
+    ///
+    /// 运行状态的核可以接受权限低于 SBI 软件的核间中断，将转交给特权软件。
+    /// 挂起状态的核可以接受核间中断以恢复运行。
+    pub fn is_ipi_allowed(&self, hart_id: usize) -> bool {
+        use core::sync::atomic::Ordering::Acquire;
+        self.state
+            .get(hart_id)
+            .map_or(false, |s| matches!(s.load(Acquire), STARTED | SUSPEND))
+    }
 }
 
 // Adapt RustSBI interface to RustSBI-QEMU's QemuHsm.

Original file line number	Diff line number	Diff line change
`@@ -9,13 +9,12 @@ use spin::Once;`
`9`	`9`
`10`	`10`	`pub(crate) struct Clint {`
`11`	`11`	`base: usize,`
`12`		`- smp: usize,`
`13`	`12`	`}`
`14`	`13`
`15`	`14`	`static CLINT: Once<Clint> = Once::new();`
`16`	`15`
`17`		`-pub(crate) fn init(base: usize, smp: usize) {`
`18`		`- CLINT.call_once(\|\| Clint { base, smp });`
	`16`	`+pub(crate) fn init(base: usize) {`
	`17`	`+ CLINT.call_once(\|\| Clint { base });`
`19`	`18`	`}`
`20`	`19`
`21`	`20`	`pub(crate) fn get() -> &'static Clint {`
`@@ -42,9 +41,9 @@ impl Clint {`
`42`	`41`	`impl Ipi for &'static Clint {`
`43`	`42`	`#[inline]`
`44`	`43`	`fn send_ipi_many(&self, hart_mask: HartMask) -> SbiRet {`
`45`		`- // println!("[rustsbi] send ipi many, {:?}", hart_mask);`
`46`		`- for i in 0..self.smp {`
`47`		`- if hart_mask.has_bit(i) {`
	`44`	`+ let hsm = crate::HSM.wait();`
	`45`	`+ for i in 0..crate::NUM_HART_MAX {`
	`46`	`+ if hart_mask.has_bit(i) && hsm.is_ipi_allowed(i) {`
`48`	`47`	`self.send_soft(i);`
`49`	`48`	`}`
`50`	`49`	`}`