Merge pull request #43 from NanaHigh/nanahigh/sdio

feat(sdio): add write block operations to sdh

Author: luojia65

bouffalo-hal/src/sdio.rs

@@ -6,6 +6,7 @@ mod nodma_sdh;
 mod ops;
 mod pad;
 mod register;
+pub mod sdcard;
 pub use config::*;
 pub use dma_sdh::*;
 pub use pad::*;

bouffalo-hal/src/sdio/dma_sdh.rs

@@ -9,7 +9,7 @@ use crate::glb;
 use core::ops::Deref;
 use core::sync::atomic::{Ordering, fence};
 use embedded_io::Write;
-use embedded_sdmmc::{Block, BlockDevice, BlockIdx};
+use embedded_sdmmc::Block;
 
 /// Managed Secure Digital Host Controller peripheral.
 pub struct Sdh<SDH, PADS, CH> {
@@ -75,8 +75,11 @@ impl<'a, SDH: Deref<Target = RegisterBlock>, PADS, CH: Deref<Target = UntypedCha
             // SDH_TX_INT_CLK_SEL.
             sdh.tx_configuration.modify(|val| val.set_tx_int_clk_sel(1));
             // SDH enable interrupt.
-            sdh.normal_interrupt_status_enable
-                .modify(|val| val.enable_buffer_read_ready());
+            sdh.normal_interrupt_status_enable.modify(|val| {
+                val.enable_buffer_read_ready()
+                    .enable_buffer_write_ready()
+                    .enable_transfer_complete()
+            });
             // SDH_Set_Timeout.
             sdh.timeout_control.modify(|val| val.set_timeout_val(0x0e));
             // SDH_Powon.
@@ -99,7 +102,7 @@ impl<'a, SDH: Deref<Target = RegisterBlock>, PADS, CH: Deref<Target = UntypedCha
 
     /// Read block from sdcard using system dma controller.
     #[inline]
-    fn read_block_sys_dma(&self, block: &mut Block, block_idx: u32) {
+    pub(crate) fn read_block_sys_dma(&self, block: &mut Block, block_idx: u32) {
         unsafe {
             // SDH_SD_TRANSFER_MODE.
             self.sdh.transfer_mode.modify(|val| {
@@ -160,38 +163,101 @@ impl<'a, SDH: Deref<Target = RegisterBlock>, PADS, CH: Deref<Target = UntypedCha
         }
     }
 
-    /// Release the SDH instance and return the pads and configs.
+    /// Write block from sdcard using system dma controller.
     #[inline]
-    pub fn free(self) -> (SDH, PADS, CH) {
-        (self.sdh, self.pads, self.dma_channel)
-    }
-}
+    pub(crate) fn write_block_sys_dma(&self, block: &Block, block_idx: u32) {
+        unsafe {
+            // SDH_SD_TRANSFER_MODE.
+            self.sdh.transfer_mode.modify(|val| {
+                val.set_data_transfer_mode(DataTransferMode::MOSI) // SDH_TO_HOST_DIR.
+                    .set_auto_cmd_mode(AutoCMDMode::None) // SDH_AUTO_CMD_EN.
+            });
 
-impl<'a, SDH: Deref<Target = RegisterBlock>, PADS, CH: Deref<Target = UntypedChannel<'a>>>
-    BlockDevice for Sdh<SDH, PADS, CH>
-{
-    type Error = core::convert::Infallible;
+            // Block_size.
+            self.sdh
+                .block_size
+                .modify(|val| val.set_transfer_block(512));
 
-    #[inline]
-    fn read(
-        &self,
-        blocks: &mut [Block],
-        start_block_idx: BlockIdx,
-        _reason: &str,
-    ) -> Result<(), Self::Error> {
-        for (i, block) in blocks.iter_mut().enumerate() {
-            self.read_block_sys_dma(block, start_block_idx.0 + i as u32);
+            // Block_count.
+            self.sdh.block_count.modify(|val| val.set_blocks_count(1));
+
+            // SDH_ClearIntStatus(SDH_INT_BUFFER_WRITE_READY).
+            self.sdh
+                .normal_interrupt_status
+                .modify(|val| val.clear_buffer_write_ready());
+        }
+        send_command(&self.sdh, SdhResp::R1, CmdType::Normal, 24, block_idx, true);
+
+        while !self
+            .sdh
+            .normal_interrupt_status
+            .read()
+            .is_buffer_write_ready()
+        {
+            // SDH_INT_BUFFER_WRITE_READY.
+            // Wait for buffer write ready.
+            core::hint::spin_loop()
+        }
+
+        for j in 0..Block::LEN / 4 {
+            let tx_lli_pool = &mut [LliPool::new(); 1];
+            let val = [
+                block[j * 4 + 0],
+                block[j * 4 + 1],
+                block[j * 4 + 2],
+                block[j * 4 + 3],
+            ];
+            let tx_transfer = &mut [LliTransfer {
+                src_addr: val.as_ptr() as u32,
+                dst_addr: 0x20060020,
+                nbytes: 4,
+            }];
+
+            self.dma_channel.lli_reload(tx_lli_pool, 1, tx_transfer, 1);
+            self.dma_channel.start();
+
+            while self.dma_channel.is_busy() {
+                core::hint::spin_loop();
+            }
+
+            self.dma_channel.stop();
+
+            // FIXME modify to a proper fence
+            fence(Ordering::SeqCst);
+
+            unsafe {
+                self.sdh
+                    .normal_interrupt_status
+                    .modify(|val| val.clear_buffer_write_ready());
+            }
+        }
+
+        // Wait for transfer completed.
+        while !self
+            .sdh
+            .normal_interrupt_status
+            .read()
+            .is_transfer_completed()
+        {
+            core::hint::spin_loop();
+        }
+
+        unsafe {
+            self.sdh
+                .normal_interrupt_status
+                .modify(|val| val.clear_transfer_completed());
         }
-        Ok(())
     }
 
+    /// Read block from sdcard using system dma controller.
     #[inline]
-    fn write(&self, _blocks: &[Block], _start_block_idx: BlockIdx) -> Result<(), Self::Error> {
-        todo!();
+    pub(crate) fn num_blocks(&self) -> embedded_sdmmc::BlockCount {
+        embedded_sdmmc::BlockCount(self.block_count)
     }
 
+    /// Release the SDH instance and return the pads and configs.
     #[inline]
-    fn num_blocks(&self) -> Result<embedded_sdmmc::BlockCount, Self::Error> {
-        Ok(embedded_sdmmc::BlockCount(self.block_count))
+    pub fn free(self) -> (SDH, PADS, CH) {
+        (self.sdh, self.pads, self.dma_channel)
     }
 }

bouffalo-hal/src/sdio/nodma_sdh.rs

@@ -1,11 +1,11 @@
 use super::config::Config;
-use super::ops::{card_init, read_block};
+use super::ops::{card_init, read_block, write_block};
 use super::pad::Pads;
 use super::register::{BusVoltage, ClkGenMode, DmaMode, RegisterBlock};
 use crate::glb;
 use core::ops::Deref;
 use embedded_io::Write;
-use embedded_sdmmc::{Block, BlockDevice, BlockIdx};
+use embedded_sdmmc::Block;
 
 /// Managed Secure Digital Host Controller peripheral.
 pub struct Sdh<SDH, PADS> {
@@ -67,8 +67,11 @@ impl<SDH: Deref<Target = RegisterBlock>, PADS> Sdh<SDH, PADS> {
             // SDH_TX_INT_CLK_SEL.
             sdh.tx_configuration.modify(|val| val.set_tx_int_clk_sel(1));
             // SDH enable interrupt.
-            sdh.normal_interrupt_status_enable
-                .modify(|val| val.enable_buffer_read_ready());
+            sdh.normal_interrupt_status_enable.modify(|val| {
+                val.enable_buffer_read_ready()
+                    .enable_buffer_write_ready()
+                    .enable_transfer_complete()
+            });
             // SDH_Set_Timeout.
             sdh.timeout_control.modify(|val| val.set_timeout_val(0x0e));
             // SDH_Powon.
@@ -88,36 +91,27 @@ impl<SDH: Deref<Target = RegisterBlock>, PADS> Sdh<SDH, PADS> {
         self.block_count = card_init(&self.sdh, w, debug)
     }
 
-    /// Release the SDH instance and return the pads and configs.
+    /// Read a block from the SDH peripheral.
     #[inline]
-    pub fn free(self) -> (SDH, PADS) {
-        (self.sdh, self.pads)
+    pub(crate) fn read_block(&self, block: &mut Block, block_idx: u32) {
+        read_block(&self.sdh, block, block_idx);
     }
-}
-
-impl<SDH: Deref<Target = RegisterBlock>, PADS> BlockDevice for Sdh<SDH, PADS> {
-    type Error = core::convert::Infallible;
 
+    /// Write a block to the SDH peripheral.
     #[inline]
-    fn read(
-        &self,
-        blocks: &mut [Block],
-        start_block_idx: BlockIdx,
-        _reason: &str,
-    ) -> Result<(), Self::Error> {
-        for (i, block) in blocks.iter_mut().enumerate() {
-            read_block(&self.sdh, block, start_block_idx.0 + i as u32);
-        }
-        Ok(())
+    pub(crate) fn write_block(&self, block: &Block, block_idx: u32) {
+        write_block(&self.sdh, block, block_idx);
     }
 
+    /// Read the block count from the SDH peripheral.
     #[inline]
-    fn write(&self, _blocks: &[Block], _start_block_idx: BlockIdx) -> Result<(), Self::Error> {
-        todo!();
+    pub(crate) fn num_blocks(&self) -> embedded_sdmmc::BlockCount {
+        embedded_sdmmc::BlockCount(self.block_count)
     }
 
+    /// Release the SDH instance and return the pads and configs.
     #[inline]
-    fn num_blocks(&self) -> Result<embedded_sdmmc::BlockCount, Self::Error> {
-        Ok(embedded_sdmmc::BlockCount(self.block_count))
+    pub fn free(self) -> (SDH, PADS) {
+        (self.sdh, self.pads)
     }
 }

bouffalo-hal/src/sdio/ops.rs

@@ -77,6 +77,60 @@ pub(crate) fn read_block(sdh: &RegisterBlock, block: &mut Block, block_idx: u32)
     }
 }
 
+#[inline]
+pub(crate) fn write_block(sdh: &RegisterBlock, block: &Block, block_idx: u32) {
+    unsafe {
+        // SDH_SD_TRANSFER_MODE.
+        sdh.transfer_mode.modify(|val| {
+            val.set_data_transfer_mode(DataTransferMode::MOSI) // SDH_TO_HOST_DIR.
+                .set_auto_cmd_mode(AutoCMDMode::None) // SDH_AUTO_CMD_EN.
+        });
+
+        // Block_size.
+        sdh.block_size.modify(|val| val.set_transfer_block(512));
+
+        // Block_count.
+        sdh.block_count.modify(|val| val.set_blocks_count(1));
+
+        // SDH_ClearIntStatus(SDH_INT_BUFFER_WRITE_READY).
+        sdh.normal_interrupt_status
+            .modify(|val| val.clear_buffer_write_ready());
+    }
+    send_command(sdh, SdhResp::R1, CmdType::Normal, 24, block_idx, true);
+
+    while !sdh.normal_interrupt_status.read().is_buffer_write_ready() {
+        // SDH_INT_BUFFER_WRITE_READY.
+        // Wait for buffer write ready.
+        core::hint::spin_loop()
+    }
+
+    for j in 0..Block::LEN / 4 {
+        let data_val = u32::from_le_bytes([
+            block[j * 4 + 0],
+            block[j * 4 + 1],
+            block[j * 4 + 2],
+            block[j * 4 + 3],
+        ]);
+
+        unsafe {
+            sdh.buffer_data_port
+                .modify(|val| val.set_buffer_data(data_val));
+            sdh.normal_interrupt_status
+                .modify(|val| val.clear_buffer_write_ready());
+        }
+    }
+
+    // Wait for transfer completed.
+    while !sdh.normal_interrupt_status.read().is_transfer_completed() {
+        core::hint::spin_loop();
+    }
+
+    unsafe {
+        sdh.normal_interrupt_status
+            .modify(|val| val.clear_transfer_completed());
+    }
+}
+
 /// Send command to sdcard.
 #[inline]
 pub(crate) fn send_command(
@@ -210,19 +264,19 @@ pub(crate) fn card_init<W: Write>(sdh: &RegisterBlock, w: &mut W, debug: bool) -
     send_command(sdh, SdhResp::R1, CmdType::Normal, 6, 0x0, false);
     sleep_ms(100);
 
-    let kb_size = (block_count as f64) * (block_size as f64) / 1024.0;
-    let mb_size = kb_size / 1024.0;
-    let gb_size = mb_size / 1024.0;
+    if debug {
+        let kb_size = (block_count as f64) * (block_size as f64) / 1024.0;
+        let mb_size = kb_size / 1024.0;
+        let gb_size = mb_size / 1024.0;
 
-    let cap = sdh.capabilities.read();
-    let version = sdh.host_controller_version.read();
+        let cap = sdh.capabilities.read();
+        let version = sdh.host_controller_version.read();
 
-    writeln!(*w, "SpecifiicVersion: {:?}", version.specific_version()).ok();
-    writeln!(*w, "SlotType: {:?}", cap.slot_type()).ok();
-    writeln!(*w, "SDMA support: {}", cap.is_sdma_supported()).ok();
-    writeln!(*w, "ADMA2 support: {}", cap.is_adma2_supported()).ok();
+        writeln!(*w, "SpecifiicVersion: {:?}", version.specific_version()).ok();
+        writeln!(*w, "SlotType: {:?}", cap.slot_type()).ok();
+        writeln!(*w, "SDMA support: {}", cap.is_sdma_supported()).ok();
+        writeln!(*w, "ADMA2 support: {}", cap.is_adma2_supported()).ok();
 
-    if debug {
         if kb_size < 1024.0 {
             writeln!(*w, "sdcard init done, size: {:.2} KB", kb_size).ok();
         } else if mb_size < 1024.0 {