Bump bitflags to 2.3.2

Author: grant0417

Cargo.toml

@@ -21,7 +21,7 @@ rust-version = "1.57" # Needed to support panic! in const fns
 
 [dependencies]
 bit_field = "0.10.1"
-bitflags = "1.3.2"
+bitflags = "2.3.2"
 volatile = "0.4.4"
 rustversion = "1.0.5"
 

src/registers/control.rs

@@ -10,6 +10,7 @@ pub struct Cr0;
 bitflags! {
     /// Configuration flags of the [`Cr0`] register.
     #[repr(transparent)]
+    #[derive(PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Clone, Copy)]
     pub struct Cr0Flags: u64 {
         /// Enables protected mode.
         const PROTECTED_MODE_ENABLE = 1;
@@ -64,6 +65,7 @@ bitflags! {
     /// Controls cache settings for the highest-level page table.
     ///
     /// Unused if paging is disabled or if [`PCID`](Cr4Flags::PCID) is enabled.
+    #[derive(PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Clone, Copy)]
     pub struct Cr3Flags: u64 {
         /// Use a writethrough cache policy for the table (otherwise a writeback policy is used).
         const PAGE_LEVEL_WRITETHROUGH = 1 << 3;
@@ -80,6 +82,7 @@ pub struct Cr4;
 bitflags! {
     /// Configuration flags of the [`Cr4`] register.
     #[repr(transparent)]
+    #[derive(PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Clone, Copy)]
     pub struct Cr4Flags: u64 {
         /// Enables hardware-supported performance enhancements for software running in
         /// virtual-8086 mode.

src/registers/debug.rs

@@ -110,6 +110,7 @@ pub struct Dr6;
 bitflags! {
     /// Debug condition flags of the [`Dr6`] register.
     #[repr(transparent)]
+    #[derive(PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Clone, Copy)]
     pub struct Dr6Flags: u64 {
         /// Breakpoint condition 0 was detected.
         const TRAP0 = 1;
@@ -124,7 +125,7 @@ bitflags! {
         const TRAP3 = 1 << 3;
 
         /// Breakpoint condition was detected.
-        const TRAP = Self::TRAP0.bits | Self::TRAP1.bits | Self::TRAP2.bits | Self::TRAP3.bits;
+        const TRAP = Self::TRAP0.bits() | Self::TRAP1.bits() | Self::TRAP2.bits() | Self::TRAP3.bits();
 
         /// Next instruction accesses one of the debug registers.
         ///
@@ -164,6 +165,7 @@ impl Dr6Flags {
 bitflags! {
     /// Debug control flags of the [`Dr7`] register.
     #[repr(transparent)]
+    #[derive(PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Clone, Copy)]
     pub struct Dr7Flags: u64 {
         /// Breakpoint 0 is enabled for the current task.
         const LOCAL_BREAKPOINT_0_ENABLE = 1;

src/registers/model_specific.rs

@@ -111,6 +111,7 @@ impl SCet {
 bitflags! {
     /// Flags of the Extended Feature Enable Register.
     #[repr(transparent)]
+    #[derive(PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Clone, Copy)]
     pub struct EferFlags: u64 {
         /// Enables the `syscall` and `sysret` instructions.
         const SYSTEM_CALL_EXTENSIONS = 1;
@@ -135,6 +136,7 @@ bitflags! {
     /// Flags stored in IA32_U_CET and IA32_S_CET (Table-2-2 in Intel SDM Volume
     /// 4). The Intel SDM-equivalent names are described in parentheses.
     #[repr(transparent)]
+    #[derive(PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Clone, Copy)]
     pub struct CetFlags: u64 {
         /// Enable shadow stack (SH_STK_EN)
         const SS_ENABLE = 1 << 0;

src/registers/mxcsr.rs

@@ -8,6 +8,7 @@ use bitflags::bitflags;
 bitflags! {
     /// MXCSR register.
     #[repr(transparent)]
+    #[derive(PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Clone, Copy)]
     pub struct MxCsr: u32 {
         /// Invalid operation
         const INVALID_OPERATION = 1 << 0;

src/registers/rflags.rs

@@ -8,6 +8,7 @@ use bitflags::bitflags;
 bitflags! {
     /// The RFLAGS register.
     #[repr(transparent)]
+    #[derive(PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Clone, Copy)]
     pub struct RFlags: u64 {
         /// Processor feature identification flag.
         ///

src/registers/xcontrol.rs

@@ -11,6 +11,7 @@ bitflags! {
     /// For MPX, [`BNDREG`](XCr0Flags::BNDREG) and [`BNDCSR`](XCr0Flags::BNDCSR) must be set/unset simultaneously.
     /// For AVX-512, [`OPMASK`](XCr0Flags::OPMASK), [`ZMM_HI256`](XCr0Flags::ZMM_HI256), and [`HI16_ZMM`](XCr0Flags::HI16_ZMM) must be set/unset simultaneously.
     #[repr(transparent)]
+    #[derive(PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Clone, Copy)]
     pub struct XCr0Flags: u64 {
         /// Enables using the x87 FPU state
         /// with `XSAVE`/`XRSTOR`.

src/structures/gdt.rs

@@ -187,6 +187,7 @@ pub enum Descriptor {
 
 bitflags! {
     /// Flags for a GDT descriptor. Not all flags are valid for all descriptor types.
+    #[derive(PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Clone, Copy)]
     pub struct DescriptorFlags: u64 {
         /// Set by the processor if this segment has been accessed. Only cleared by software.
         /// _Setting_ this bit in software prevents GDT writes on first use.

src/structures/idt.rs

@@ -968,6 +968,7 @@ bitflags! {
     ///   * AMD Volume 2: 8.4.2
     ///   * Intel Volume 3A: 4.7
     #[repr(transparent)]
+    #[derive(PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Clone, Copy)]
     pub struct PageFaultErrorCode: u64 {
         /// If this flag is set, the page fault was caused by a page-protection violation,
         /// else the page fault was caused by a not-present page.

src/structures/paging/page_table.rs

@@ -106,6 +106,7 @@ impl fmt::Debug for PageTableEntry {
 
 bitflags! {
     /// Possible flags for a page table entry.
+    #[derive(PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Clone, Copy)]
     pub struct PageTableFlags: u64 {
         /// Specifies whether the mapped frame or page table is loaded in memory.
         const PRESENT =         1;