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1 parent b1780e1 commit 472d863Copy full SHA for 472d863
src/registers/control.rs
@@ -326,6 +326,21 @@ mod x86_64 {
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}
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+ /// Write a new P4 table address into the CR3 register without flushing existing TLB entries for
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+ /// the PCID.
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+ ///
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+ /// ## Safety
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+ /// Changing the level 4 page table is unsafe, because it's possible to violate memory safety by
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+ /// changing the page mapping.
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+ /// [`Cr4Flags::PCID`] must be set before calling this method.
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+ #[inline]
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+ pub unsafe fn write_pcid_no_flush(frame: PhysFrame, pcid: Pcid) {
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+ unsafe {
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+ Cr3::write_raw_impl(true, frame, pcid.value());
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+ }
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+
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/// Write a new P4 table address into the CR3 register.
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///
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/// ## Safety
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