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Merge pull request #476 from mkroening/clippy-fix
fix and detect warnings
2 parents b70e8bc + 2eb838d commit 2b813b2

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15 files changed

+48
-16
lines changed

15 files changed

+48
-16
lines changed

.github/workflows/build.yml

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@@ -14,6 +14,7 @@ permissions:
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contents: read
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env:
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RUSTFLAGS: -Dwarnings
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RUSTDOCFLAGS: -Dwarnings
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jobs:

src/addr.rs

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@@ -240,6 +240,7 @@ impl VirtAddr {
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}
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// FIXME: Move this into the `Step` impl, once `Step` is stabilized.
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#[cfg(any(feature = "instructions", feature = "step_trait"))]
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pub(crate) fn steps_between_impl(start: &Self, end: &Self) -> Option<usize> {
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let mut steps = end.0.checked_sub(start.0)?;
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src/instructions/random.rs

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@@ -65,7 +65,7 @@ impl RdRand {
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}
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}
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#[cfg(all(test))]
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#[cfg(test)]
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mod tests {
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use super::*;
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src/registers/control.rs

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@@ -296,7 +296,7 @@ mod x86_64 {
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#[inline]
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pub fn read_pcid() -> (PhysFrame, Pcid) {
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let (frame, value) = Cr3::read_raw();
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(frame, Pcid::new(value as u16).unwrap())
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(frame, Pcid::new(value).unwrap())
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}
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/// Write a new P4 table address into the CR3 register.

src/registers/model_specific.rs

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@@ -6,6 +6,7 @@ use bitflags::bitflags;
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use crate::registers::segmentation::{FS, GS};
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/// A model specific register.
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#[cfg_attr(not(feature = "instructions"), allow(dead_code))] // FIXME
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#[derive(Debug)]
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pub struct Msr(u32);
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src/structures/gdt.rs

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@@ -117,6 +117,13 @@ impl GlobalDescriptorTable {
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}
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}
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impl Default for GlobalDescriptorTable {
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#[inline]
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fn default() -> Self {
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Self::new()
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}
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}
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impl<const MAX: usize> GlobalDescriptorTable<MAX> {
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/// Creates an empty GDT which can hold `MAX` number of [`Entry`]s.
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#[inline]

src/structures/idt.rs

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@@ -565,6 +565,13 @@ impl InterruptDescriptorTable {
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}
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}
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impl Default for InterruptDescriptorTable {
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#[inline]
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fn default() -> Self {
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Self::new()
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}
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}
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impl Index<u8> for InterruptDescriptorTable {
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type Output = Entry<HandlerFunc>;
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src/structures/paging/mapper/mapped_page_table.rs

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@@ -1,9 +1,7 @@
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use crate::structures::paging::{
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frame::PhysFrame,
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frame_alloc::{FrameAllocator, FrameDeallocator},
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mapper::*,
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page::{AddressNotAligned, Page, PageRangeInclusive, Size1GiB, Size2MiB, Size4KiB},
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page_table::{FrameError, PageTable, PageTableEntry, PageTableFlags, PageTableLevel},
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page::AddressNotAligned,
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page_table::{FrameError, PageTable, PageTableEntry, PageTableLevel},
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};
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/// A Mapper implementation that relies on a PhysAddr to VirtAddr conversion function.
@@ -549,6 +547,7 @@ impl<'a, P: PageTableFrameMapping> Translate for MappedPageTable<'a, P> {
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Err(PageTableWalkError::MappedToHugePage) => {
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let entry = &p3[addr.p3_index()];
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let frame = PhysFrame::containing_address(entry.addr());
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#[allow(clippy::unusual_byte_groupings)]
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let offset = addr.as_u64() & 0o_777_777_7777;
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let flags = entry.flags();
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return TranslateResult::Mapped {
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Err(PageTableWalkError::MappedToHugePage) => {
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let entry = &p2[addr.p2_index()];
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let frame = PhysFrame::containing_address(entry.addr());
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#[allow(clippy::unusual_byte_groupings)]
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let offset = addr.as_u64() & 0o_777_7777;
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let flags = entry.flags();
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return TranslateResult::Mapped {

src/structures/paging/mapper/mod.rs

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@@ -383,6 +383,7 @@ pub trait Mapper<S: PageSize> {
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/// changed the mapping of a page to ensure that the TLB flush is not forgotten.
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#[derive(Debug)]
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#[must_use = "Page Table changes must be flushed or ignored."]
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#[cfg_attr(not(feature = "instructions"), allow(dead_code))] // FIXME
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pub struct MapperFlush<S: PageSize>(Page<S>);
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impl<S: PageSize> MapperFlush<S> {

src/structures/paging/mapper/offset_page_table.rs

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@@ -1,9 +1,6 @@
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#![cfg(target_pointer_width = "64")]
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use crate::structures::paging::{
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frame::PhysFrame, mapper::*, page::PageRangeInclusive, page_table::PageTable, FrameDeallocator,
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Page, PageTableFlags,
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};
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use crate::structures::paging::{mapper::*, page_table::PageTable};
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/// A Mapper implementation that requires that the complete physically memory is mapped at some
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/// offset in the virtual address space.

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