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AmanieuAmanieu
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Add tracking issues for feature detection
1 parent bf72b03 commit c619e83

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-77
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10 files changed

+89
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‎crates/std_detect/src/detect/arch/arm.rs

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -6,23 +6,23 @@ features! {
66
@MACRO_NAME: is_arm_feature_detected;
77
@MACRO_ATTRS:
88
/// Checks if `arm` feature is enabled.
9-
#[unstable(feature = "stdsimd", issue = "27731")]
9+
#[unstable(feature = "stdarch_arm_feature_detection", issue = "111190")]
1010
@NO_RUNTIME_DETECTION: "v7";
1111
@NO_RUNTIME_DETECTION: "vfp2";
1212
@NO_RUNTIME_DETECTION: "vfp3";
1313
@NO_RUNTIME_DETECTION: "vfp4";
14-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] neon: "neon";
14+
@FEATURE: #[unstable(feature = "stdarch_arm_feature_detection", issue = "111190")] neon: "neon";
1515
/// ARM Advanced SIMD (NEON) - Aarch32
16-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] pmull: "pmull";
16+
@FEATURE: #[unstable(feature = "stdarch_arm_feature_detection", issue = "111190")] pmull: "pmull";
1717
/// Polynomial Multiply
18-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] crc: "crc";
18+
@FEATURE: #[unstable(feature = "stdarch_arm_feature_detection", issue = "111190")] crc: "crc";
1919
/// CRC32 (Cyclic Redundancy Check)
20-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] aes: "aes";
20+
@FEATURE: #[unstable(feature = "stdarch_arm_feature_detection", issue = "111190")] aes: "aes";
2121
/// FEAT_AES (AES instructions)
22-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] sha2: "sha2";
22+
@FEATURE: #[unstable(feature = "stdarch_arm_feature_detection", issue = "111190")] sha2: "sha2";
2323
/// FEAT_SHA1 & FEAT_SHA256 (SHA1 & SHA2-256 instructions)
24-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] i8mm: "i8mm";
24+
@FEATURE: #[unstable(feature = "stdarch_arm_feature_detection", issue = "111190")] i8mm: "i8mm";
2525
/// FEAT_I8MM (integer matrix multiplication, plus ASIMD support)
26-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] dotprod: "dotprod";
26+
@FEATURE: #[unstable(feature = "stdarch_arm_feature_detection", issue = "111190")] dotprod: "dotprod";
2727
/// FEAT_DotProd (Vector Dot-Product - ASIMDDP)
2828
}

‎crates/std_detect/src/detect/arch/mips.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ features! {
66
@MACRO_NAME: is_mips_feature_detected;
77
@MACRO_ATTRS:
88
/// Checks if `mips` feature is enabled.
9-
#[unstable(feature = "stdsimd", issue = "27731")]
10-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] msa: "msa";
9+
#[unstable(feature = "stdarch_mips_feature_detection", issue = "111188")]
10+
@FEATURE: #[unstable(feature = "stdarch_mips_feature_detection", issue = "111188")] msa: "msa";
1111
/// MIPS SIMD Architecture (MSA)
1212
}

‎crates/std_detect/src/detect/arch/mips64.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ features! {
66
@MACRO_NAME: is_mips64_feature_detected;
77
@MACRO_ATTRS:
88
/// Checks if `mips64` feature is enabled.
9-
#[unstable(feature = "stdsimd", issue = "27731")]
10-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] msa: "msa";
9+
#[unstable(feature = "stdarch_mips_feature_detection", issue = "111188")]
10+
@FEATURE: #[unstable(feature = "stdarch_mips_feature_detection", issue = "111188")] msa: "msa";
1111
/// MIPS SIMD Architecture (MSA)
1212
}

‎crates/std_detect/src/detect/arch/mod.rs

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,20 +22,28 @@ mod mips64;
2222

2323
cfg_if! {
2424
if #[cfg(any(target_arch = "x86", target_arch = "x86_64"))] {
25+
#[stable(feature = "simd_x86", since = "1.27.0")]
2526
pub use x86::*;
2627
} else if #[cfg(target_arch = "arm")] {
28+
#[unstable(feature = "stdarch_arm_feature_detection", issue = "111190")]
2729
pub use arm::*;
2830
} else if #[cfg(target_arch = "aarch64")] {
31+
#[stable(feature = "simd_aarch64", since = "1.60.0")]
2932
pub use aarch64::*;
3033
} else if #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))] {
34+
#[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")]
3135
pub use riscv::*;
3236
} else if #[cfg(target_arch = "powerpc")] {
37+
#[unstable(feature = "stdarch_powerpc_feature_detection", issue = "111191")]
3338
pub use powerpc::*;
3439
} else if #[cfg(target_arch = "powerpc64")] {
40+
#[unstable(feature = "stdarch_powerpc_feature_detection", issue = "111191")]
3541
pub use powerpc64::*;
3642
} else if #[cfg(target_arch = "mips")] {
43+
#[unstable(feature = "stdarch_mips_feature_detection", issue = "111188")]
3744
pub use mips::*;
3845
} else if #[cfg(target_arch = "mips64")] {
46+
#[unstable(feature = "stdarch_mips_feature_detection", issue = "111188")]
3947
pub use mips64::*;
4048
} else {
4149
// Unimplemented architecture:
@@ -44,6 +52,7 @@ cfg_if! {
4452
Null
4553
}
4654
#[doc(hidden)]
55+
#[unstable(feature = "stdarch_internal", issue = "none")]
4756
pub mod __is_feature_detected {}
4857

4958
impl Feature {

‎crates/std_detect/src/detect/arch/powerpc.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -6,11 +6,11 @@ features! {
66
@MACRO_NAME: is_powerpc_feature_detected;
77
@MACRO_ATTRS:
88
/// Checks if `powerpc` feature is enabled.
9-
#[unstable(feature = "stdsimd", issue = "27731")]
10-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] altivec: "altivec";
9+
#[unstable(feature = "stdarch_powerpc_feature_detection", issue = "111191")]
10+
@FEATURE: #[unstable(feature = "stdarch_powerpc_feature_detection", issue = "111191")] altivec: "altivec";
1111
/// Altivec
12-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] vsx: "vsx";
12+
@FEATURE: #[unstable(feature = "stdarch_powerpc_feature_detection", issue = "111191")] vsx: "vsx";
1313
/// VSX
14-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] power8: "power8";
14+
@FEATURE: #[unstable(feature = "stdarch_powerpc_feature_detection", issue = "111191")] power8: "power8";
1515
/// Power8
1616
}

‎crates/std_detect/src/detect/arch/powerpc64.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -6,11 +6,11 @@ features! {
66
@MACRO_NAME: is_powerpc64_feature_detected;
77
@MACRO_ATTRS:
88
/// Checks if `powerpc` feature is enabled.
9-
#[unstable(feature = "stdsimd", issue = "27731")]
10-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] altivec: "altivec";
9+
#[unstable(feature = "stdarch_powerpc_feature_detection", issue = "111191")]
10+
@FEATURE: #[unstable(feature = "stdarch_powerpc_feature_detection", issue = "111191")] altivec: "altivec";
1111
/// Altivec
12-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] vsx: "vsx";
12+
@FEATURE: #[unstable(feature = "stdarch_powerpc_feature_detection", issue = "111191")] vsx: "vsx";
1313
/// VSX
14-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] power8: "power8";
14+
@FEATURE: #[unstable(feature = "stdarch_powerpc_feature_detection", issue = "111191")] power8: "power8";
1515
/// Power8
1616
}

‎crates/std_detect/src/detect/arch/riscv.rs

Lines changed: 50 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -99,108 +99,108 @@ features! {
9999
/// * Zkt: `"zkt"`
100100
///
101101
/// [ISA manual]: https://github.com/riscv/riscv-isa-manual/
102-
#[unstable(feature = "stdsimd", issue = "27731")]
103-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv32i: "rv32i";
102+
#[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")]
103+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32i: "rv32i";
104104
/// RV32I Base Integer Instruction Set
105-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zifencei: "zifencei";
105+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zifencei: "zifencei";
106106
/// "Zifencei" Instruction-Fetch Fence
107-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zihintpause: "zihintpause";
107+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihintpause: "zihintpause";
108108
/// "Zihintpause" Pause Hint
109-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv64i: "rv64i";
109+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv64i: "rv64i";
110110
/// RV64I Base Integer Instruction Set
111-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] m: "m";
111+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] m: "m";
112112
/// "M" Standard Extension for Integer Multiplication and Division
113-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] a: "a";
113+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] a: "a";
114114
/// "A" Standard Extension for Atomic Instructions
115-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zicsr: "zicsr";
115+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicsr: "zicsr";
116116
/// "Zicsr", Control and Status Register (CSR) Instructions
117-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zicntr: "zicntr";
117+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicntr: "zicntr";
118118
/// "Zicntr", Standard Extension for Base Counters and Timers
119-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zihpm: "zihpm";
119+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihpm: "zihpm";
120120
/// "Zihpm", Standard Extension for Hardware Performance Counters
121-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] f: "f";
121+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] f: "f";
122122
/// "F" Standard Extension for Single-Precision Floating-Point
123-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] d: "d";
123+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] d: "d";
124124
/// "D" Standard Extension for Double-Precision Floating-Point
125-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] q: "q";
125+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] q: "q";
126126
/// "Q" Standard Extension for Quad-Precision Floating-Point
127-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] c: "c";
127+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] c: "c";
128128
/// "C" Standard Extension for Compressed Instructions
129129
130-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zfinx: "zfinx";
130+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfinx: "zfinx";
131131
/// "Zfinx" Standard Extension for Single-Precision Floating-Point in Integer Registers
132-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zdinx: "zdinx";
132+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zdinx: "zdinx";
133133
/// "Zdinx" Standard Extension for Double-Precision Floating-Point in Integer Registers
134-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zhinx: "zhinx";
134+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zhinx: "zhinx";
135135
/// "Zhinx" Standard Extension for Half-Precision Floating-Point in Integer Registers
136-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zhinxmin: "zhinxmin";
136+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zhinxmin: "zhinxmin";
137137
/// "Zhinxmin" Standard Extension for Minimal Half-Precision Floating-Point in Integer Registers
138-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] ztso: "ztso";
138+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] ztso: "ztso";
139139
/// "Ztso" Standard Extension for Total Store Ordering
140140
141-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv32e: "rv32e";
141+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32e: "rv32e";
142142
/// RV32E Base Integer Instruction Set
143-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] rv128i: "rv128i";
143+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv128i: "rv128i";
144144
/// RV128I Base Integer Instruction Set
145-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zfh: "zfh";
145+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfh: "zfh";
146146
/// "Zfh" Standard Extension for 16-Bit Half-Precision Floating-Point
147-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zfhmin: "zfhmin";
147+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfhmin: "zfhmin";
148148
/// "Zfhmin" Standard Extension for Minimal Half-Precision Floating-Point Support
149-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] b: "b";
149+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] b: "b";
150150
/// "B" Standard Extension for Bit Manipulation
151-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] j: "j";
151+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] j: "j";
152152
/// "J" Standard Extension for Dynamically Translated Languages
153-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] p: "p";
153+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] p: "p";
154154
/// "P" Standard Extension for Packed-SIMD Instructions
155-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] v: "v";
155+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] v: "v";
156156
/// "V" Standard Extension for Vector Operations
157-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zam: "zam";
157+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zam: "zam";
158158
/// "Zam" Standard Extension for Misaligned Atomics
159159
160-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] s: "s";
160+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] s: "s";
161161
/// Supervisor-Level ISA
162-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] svnapot: "svnapot";
162+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svnapot: "svnapot";
163163
/// "Svnapot" Standard Extension for NAPOT Translation Contiguity
164-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] svpbmt: "svpbmt";
164+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svpbmt: "svpbmt";
165165
/// "Svpbmt" Standard Extension for Page-Based Memory Types
166-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] svinval: "svinval";
166+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svinval: "svinval";
167167
/// "Svinval" Standard Extension for Fine-Grained Address-Translation Cache Invalidation
168-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] h: "h";
168+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] h: "h";
169169
/// Hypervisor Extension
170170
171-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zba: "zba";
171+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zba: "zba";
172172
/// "Zba" Standard Extension for Address Generation Instructions
173-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbb: "zbb";
173+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbb: "zbb";
174174
/// "Zbb" Standard Extension for Basic Bit-Manipulation
175-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbc: "zbc";
175+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbc: "zbc";
176176
/// "Zbc" Standard Extension for Carry-less Multiplication
177-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbs: "zbs";
177+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbs: "zbs";
178178
/// "Zbs" Standard Extension for Single-Bit instructions
179179
180-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbkb: "zbkb";
180+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbkb: "zbkb";
181181
/// "Zbkb" Standard Extension for Bitmanip instructions for Cryptography
182-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbkc: "zbkc";
182+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbkc: "zbkc";
183183
/// "Zbkc" Standard Extension for Carry-less multiply instructions
184-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zbkx: "zbkx";
184+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zbkx: "zbkx";
185185
/// "Zbkx" Standard Extension for Crossbar permutation instructions
186-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zknd: "zknd";
186+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zknd: "zknd";
187187
/// "Zknd" Standard Extension for NIST Suite: AES Decryption
188-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkne: "zkne";
188+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zkne: "zkne";
189189
/// "Zkne" Standard Extension for NIST Suite: AES Encryption
190-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zknh: "zknh";
190+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zknh: "zknh";
191191
/// "Zknh" Standard Extension for NIST Suite: Hash Function Instructions
192-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zksed: "zksed";
192+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zksed: "zksed";
193193
/// "Zksed" Standard Extension for ShangMi Suite: SM4 Block Cipher Instructions
194-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zksh: "zksh";
194+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zksh: "zksh";
195195
/// "Zksh" Standard Extension for ShangMi Suite: SM3 Hash Function Instructions
196-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkr: "zkr";
196+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zkr: "zkr";
197197
/// "Zkr" Standard Extension for Entropy Source Extension
198-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkn: "zkn";
198+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zkn: "zkn";
199199
/// "Zkn" Standard Extension for NIST Algorithm Suite
200-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zks: "zks";
200+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zks: "zks";
201201
/// "Zks" Standard Extension for ShangMi Algorithm Suite
202-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zk: "zk";
202+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zk: "zk";
203203
/// "Zk" Standard Extension for Standard scalar cryptography extension
204-
@FEATURE: #[unstable(feature = "stdsimd", issue = "27731")] zkt: "zkt";
204+
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zkt: "zkt";
205205
/// "Zkt" Standard Extension for Data Independent Execution Latency
206206
}

‎crates/std_detect/src/detect/macros.rs

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
#[macro_export]
2-
#[allow_internal_unstable(stdsimd)]
2+
#[allow_internal_unstable(stdarch_internal)]
3+
#[unstable(feature = "stdarch_internal", issue = "none")]
34
macro_rules! detect_feature {
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($feature:tt, $feature_lit:tt) => {
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$crate::detect_feature!($feature, $feature_lit : $feature_lit)
@@ -25,7 +26,7 @@ macro_rules! features {
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) => {
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#[macro_export]
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$(#[$macro_attrs])*
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#[allow_internal_unstable(stdsimd_internal, stdsimd)]
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#[allow_internal_unstable(stdarch_internal, stdsimd)]
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#[cfg($cfg)]
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#[doc(cfg($cfg))]
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macro_rules! $macro_name {
@@ -120,7 +121,7 @@ macro_rules! features {
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#[allow(non_camel_case_types)]
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#[derive(Copy, Clone)]
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#[repr(u8)]
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#[unstable(feature = "stdsimd_internal", issue = "none")]
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#[unstable(feature = "stdarch_internal", issue = "none")]
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#[cfg($cfg)]
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pub(crate) enum Feature {
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$(
@@ -157,6 +158,7 @@ macro_rules! features {
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/// to change.
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#[doc(hidden)]
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#[cfg($cfg)]
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#[unstable(feature = "stdarch_internal", issue = "none")]
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pub mod __is_feature_detected {
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$(
162164

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