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18 files changed

+156
-160
lines changed

‎coresimd/arm/mod.rs

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -20,10 +20,7 @@ mod v7;
2020
#[cfg(any(target_arch = "aarch64", target_feature = "v7"))]
2121
pub use self::v7::*;
2222

23-
#[cfg(any(
24-
all(target_feature = "v7", not(target_feature = "mclass")),
25-
dox
26-
))]
23+
#[cfg(any(all(target_feature = "v7", not(target_feature = "mclass")), dox))]
2724
mod dsp;
2825
#[cfg(any(
2926
all(target_feature = "v7", not(target_feature = "mclass")),

‎coresimd/arm/neon.rs

Lines changed: 11 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -111,10 +111,7 @@ extern "C" {
111111
target_arch = "aarch64",
112112
link_name = "llvm.aarch64.neon.frsqrte.v2f32"
113113
)]
114-
#[cfg_attr(
115-
target_arch = "arm",
116-
link_name = "llvm.arm.neon.vrsqrte.v2f32"
117-
)]
114+
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v2f32")]
118115
fn frsqrte_v2f32(a: float32x2_t) -> float32x2_t;
119116

120117
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v8i8")]
@@ -123,19 +120,13 @@ extern "C" {
123120
link_name = "llvm.aarch64.neon.sminp.v8i8"
124121
)]
125122
fn vpmins_v8i8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
126-
#[cfg_attr(
127-
target_arch = "arm",
128-
link_name = "llvm.arm.neon.vpmins.v4i16"
129-
)]
123+
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v4i16")]
130124
#[cfg_attr(
131125
target_arch = "aarch64",
132126
link_name = "llvm.aarch64.neon.sminp.v4i16"
133127
)]
134128
fn vpmins_v4i16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
135-
#[cfg_attr(
136-
target_arch = "arm",
137-
link_name = "llvm.arm.neon.vpmins.v2i32"
138-
)]
129+
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2i32")]
139130
#[cfg_attr(
140131
target_arch = "aarch64",
141132
link_name = "llvm.aarch64.neon.sminp.v2i32"
@@ -147,28 +138,19 @@ extern "C" {
147138
link_name = "llvm.aarch64.neon.uminp.v8i8"
148139
)]
149140
fn vpminu_v8i8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
150-
#[cfg_attr(
151-
target_arch = "arm",
152-
link_name = "llvm.arm.neon.vpminu.v4i16"
153-
)]
141+
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v4i16")]
154142
#[cfg_attr(
155143
target_arch = "aarch64",
156144
link_name = "llvm.aarch64.neon.uminp.v4i16"
157145
)]
158146
fn vpminu_v4i16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
159-
#[cfg_attr(
160-
target_arch = "arm",
161-
link_name = "llvm.arm.neon.vpminu.v2i32"
162-
)]
147+
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpminu.v2i32")]
163148
#[cfg_attr(
164149
target_arch = "aarch64",
165150
link_name = "llvm.aarch64.neon.uminp.v2i32"
166151
)]
167152
fn vpminu_v2i32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
168-
#[cfg_attr(
169-
target_arch = "arm",
170-
link_name = "llvm.arm.neon.vpmins.v2f32"
171-
)]
153+
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmins.v2f32")]
172154
#[cfg_attr(
173155
target_arch = "aarch64",
174156
link_name = "llvm.aarch64.neon.fminp.v2f32"
@@ -181,19 +163,13 @@ extern "C" {
181163
link_name = "llvm.aarch64.neon.smaxp.v8i8"
182164
)]
183165
fn vpmaxs_v8i8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
184-
#[cfg_attr(
185-
target_arch = "arm",
186-
link_name = "llvm.arm.neon.vpmaxs.v4i16"
187-
)]
166+
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v4i16")]
188167
#[cfg_attr(
189168
target_arch = "aarch64",
190169
link_name = "llvm.aarch64.neon.smaxp.v4i16"
191170
)]
192171
fn vpmaxs_v4i16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
193-
#[cfg_attr(
194-
target_arch = "arm",
195-
link_name = "llvm.arm.neon.vpmaxs.v2i32"
196-
)]
172+
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2i32")]
197173
#[cfg_attr(
198174
target_arch = "aarch64",
199175
link_name = "llvm.aarch64.neon.smaxp.v2i32"
@@ -205,28 +181,19 @@ extern "C" {
205181
link_name = "llvm.aarch64.neon.umaxp.v8i8"
206182
)]
207183
fn vpmaxu_v8i8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
208-
#[cfg_attr(
209-
target_arch = "arm",
210-
link_name = "llvm.arm.neon.vpmaxu.v4i16"
211-
)]
184+
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v4i16")]
212185
#[cfg_attr(
213186
target_arch = "aarch64",
214187
link_name = "llvm.aarch64.neon.umaxp.v4i16"
215188
)]
216189
fn vpmaxu_v4i16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
217-
#[cfg_attr(
218-
target_arch = "arm",
219-
link_name = "llvm.arm.neon.vpmaxu.v2i32"
220-
)]
190+
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxu.v2i32")]
221191
#[cfg_attr(
222192
target_arch = "aarch64",
223193
link_name = "llvm.aarch64.neon.umaxp.v2i32"
224194
)]
225195
fn vpmaxu_v2i32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
226-
#[cfg_attr(
227-
target_arch = "arm",
228-
link_name = "llvm.arm.neon.vpmaxs.v2f32"
229-
)]
196+
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpmaxs.v2f32")]
230197
#[cfg_attr(
231198
target_arch = "aarch64",
232199
link_name = "llvm.aarch64.neon.fmaxp.v2f32"

‎coresimd/wasm32/atomic.rs

Lines changed: 16 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -33,8 +33,8 @@ extern "C" {
3333
/// the calling thread will be blocked forever.
3434
///
3535
/// The calling thread can only be woken up with a call to the `wake` intrinsic
36-
/// once it has been blocked. Changing the memory behind `ptr` will not wake the
37-
/// thread once it's blocked.
36+
/// once it has been blocked. Changing the memory behind `ptr` will not wake
37+
/// the thread once it's blocked.
3838
///
3939
/// # Return value
4040
///
@@ -47,13 +47,15 @@ extern "C" {
4747
///
4848
/// This intrinsic is only available **when the standard library itself is
4949
/// compiled with the `atomics` target feature**. This version of the standard
50-
/// library is not obtainable via `rustup`, but rather will require the standard
51-
/// library to be compiled from source.
50+
/// library is not obtainable via `rustup`, but rather will require the
51+
/// standard library to be compiled from source.
5252
///
5353
/// [instr]: https://github.com/WebAssembly/threads/blob/master/proposals/threads/Overview.md#wait
5454
#[inline]
5555
#[cfg_attr(test, assert_instr("i32.atomic.wait"))]
56-
pub unsafe fn wait_i32(ptr: *mut i32, expression: i32, timeout_ns: i64) -> i32 {
56+
pub unsafe fn wait_i32(
57+
ptr: *mut i32, expression: i32, timeout_ns: i64,
58+
) -> i32 {
5759
llvm_atomic_wait_i32(ptr, expression, timeout_ns)
5860
}
5961

@@ -68,8 +70,8 @@ pub unsafe fn wait_i32(ptr: *mut i32, expression: i32, timeout_ns: i64) -> i32 {
6870
/// the calling thread will be blocked forever.
6971
///
7072
/// The calling thread can only be woken up with a call to the `wake` intrinsic
71-
/// once it has been blocked. Changing the memory behind `ptr` will not wake the
72-
/// thread once it's blocked.
73+
/// once it has been blocked. Changing the memory behind `ptr` will not wake
74+
/// the thread once it's blocked.
7375
///
7476
/// # Return value
7577
///
@@ -82,13 +84,15 @@ pub unsafe fn wait_i32(ptr: *mut i32, expression: i32, timeout_ns: i64) -> i32 {
8284
///
8385
/// This intrinsic is only available **when the standard library itself is
8486
/// compiled with the `atomics` target feature**. This version of the standard
85-
/// library is not obtainable via `rustup`, but rather will require the standard
86-
/// library to be compiled from source.
87+
/// library is not obtainable via `rustup`, but rather will require the
88+
/// standard library to be compiled from source.
8789
///
8890
/// [instr]: https://github.com/WebAssembly/threads/blob/master/proposals/threads/Overview.md#wait
8991
#[inline]
9092
#[cfg_attr(test, assert_instr("i64.atomic.wait"))]
91-
pub unsafe fn wait_i64(ptr: *mut i64, expression: i64, timeout_ns: i64) -> i32 {
93+
pub unsafe fn wait_i64(
94+
ptr: *mut i64, expression: i64, timeout_ns: i64,
95+
) -> i32 {
9296
llvm_atomic_wait_i64(ptr, expression, timeout_ns)
9397
}
9498

@@ -110,8 +114,8 @@ pub unsafe fn wait_i64(ptr: *mut i64, expression: i64, timeout_ns: i64) -> i32 {
110114
///
111115
/// This intrinsic is only available **when the standard library itself is
112116
/// compiled with the `atomics` target feature**. This version of the standard
113-
/// library is not obtainable via `rustup`, but rather will require the standard
114-
/// library to be compiled from source.
117+
/// library is not obtainable via `rustup`, but rather will require the
118+
/// standard library to be compiled from source.
115119
///
116120
/// [instr]: https://github.com/WebAssembly/threads/blob/master/proposals/threads/Overview.md#wake
117121
#[inline]

‎coresimd/wasm32/simd128.rs

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -635,7 +635,8 @@ impl v128 {
635635
const C: [ImmByte; 16] = unsafe {
636636
U {
637637
v: ::_core::u128::MAX,
638-
}.c
638+
}
639+
.c
639640
};
640641
Self::xor(v128::const_(C), a)
641642
}

‎coresimd/x86/avx.rs

Lines changed: 24 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1078,8 +1078,10 @@ pub unsafe fn _mm256_cvttps_epi32(a: __m256) -> __m256i {
10781078
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_extractf128_ps)
10791079
#[inline]
10801080
#[target_feature(enable = "avx")]
1081-
#[cfg_attr(all(test, not(target_os = "windows")),
1082-
assert_instr(vextractf128, imm8 = 1))]
1081+
#[cfg_attr(
1082+
all(test, not(target_os = "windows")),
1083+
assert_instr(vextractf128, imm8 = 1)
1084+
)]
10831085
#[rustc_args_required_const(1)]
10841086
#[stable(feature = "simd_x86", since = "1.27.0")]
10851087
pub unsafe fn _mm256_extractf128_ps(a: __m256, imm8: i32) -> __m128 {
@@ -1095,8 +1097,10 @@ pub unsafe fn _mm256_extractf128_ps(a: __m256, imm8: i32) -> __m128 {
10951097
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_extractf128_pd)
10961098
#[inline]
10971099
#[target_feature(enable = "avx")]
1098-
#[cfg_attr(all(test, not(target_os = "windows")),
1099-
assert_instr(vextractf128, imm8 = 1))]
1100+
#[cfg_attr(
1101+
all(test, not(target_os = "windows")),
1102+
assert_instr(vextractf128, imm8 = 1)
1103+
)]
11001104
#[rustc_args_required_const(1)]
11011105
#[stable(feature = "simd_x86", since = "1.27.0")]
11021106
pub unsafe fn _mm256_extractf128_pd(a: __m256d, imm8: i32) -> __m128d {
@@ -1111,8 +1115,10 @@ pub unsafe fn _mm256_extractf128_pd(a: __m256d, imm8: i32) -> __m128d {
11111115
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_extractf128_si256)
11121116
#[inline]
11131117
#[target_feature(enable = "avx")]
1114-
#[cfg_attr(all(test, not(target_os = "windows")),
1115-
assert_instr(vextractf128, imm8 = 1))]
1118+
#[cfg_attr(
1119+
all(test, not(target_os = "windows")),
1120+
assert_instr(vextractf128, imm8 = 1)
1121+
)]
11161122
#[rustc_args_required_const(1)]
11171123
#[stable(feature = "simd_x86", since = "1.27.0")]
11181124
pub unsafe fn _mm256_extractf128_si256(a: __m256i, imm8: i32) -> __m128i {
@@ -1513,8 +1519,10 @@ pub unsafe fn _mm256_broadcast_pd(a: &__m128d) -> __m256d {
15131519
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_insertf128_ps)
15141520
#[inline]
15151521
#[target_feature(enable = "avx")]
1516-
#[cfg_attr(all(test, not(target_os = "windows")),
1517-
assert_instr(vinsertf128, imm8 = 1))]
1522+
#[cfg_attr(
1523+
all(test, not(target_os = "windows")),
1524+
assert_instr(vinsertf128, imm8 = 1)
1525+
)]
15181526
#[rustc_args_required_const(2)]
15191527
#[stable(feature = "simd_x86", since = "1.27.0")]
15201528
pub unsafe fn _mm256_insertf128_ps(a: __m256, b: __m128, imm8: i32) -> __m256 {
@@ -1532,8 +1540,10 @@ pub unsafe fn _mm256_insertf128_ps(a: __m256, b: __m128, imm8: i32) -> __m256 {
15321540
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_insertf128_pd)
15331541
#[inline]
15341542
#[target_feature(enable = "avx")]
1535-
#[cfg_attr(all(test, not(target_os = "windows")),
1536-
assert_instr(vinsertf128, imm8 = 1))]
1543+
#[cfg_attr(
1544+
all(test, not(target_os = "windows")),
1545+
assert_instr(vinsertf128, imm8 = 1)
1546+
)]
15371547
#[rustc_args_required_const(2)]
15381548
#[stable(feature = "simd_x86", since = "1.27.0")]
15391549
pub unsafe fn _mm256_insertf128_pd(
@@ -1551,8 +1561,10 @@ pub unsafe fn _mm256_insertf128_pd(
15511561
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_insertf128_si256)
15521562
#[inline]
15531563
#[target_feature(enable = "avx")]
1554-
#[cfg_attr(all(test, not(target_os = "windows")),
1555-
assert_instr(vinsertf128, imm8 = 1))]
1564+
#[cfg_attr(
1565+
all(test, not(target_os = "windows")),
1566+
assert_instr(vinsertf128, imm8 = 1)
1567+
)]
15561568
#[rustc_args_required_const(2)]
15571569
#[stable(feature = "simd_x86", since = "1.27.0")]
15581570
pub unsafe fn _mm256_insertf128_si256(

‎coresimd/x86/avx2.rs

Lines changed: 33 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -508,8 +508,8 @@ pub unsafe fn _mm256_blend_epi16(
508508
a,
509509
b,
510510
[
511-
$a, $b, $c, $d, $e, $f, $g, $h, $i, $j, $k, $l, $m,
512-
$n, $o, $p,
511+
$a, $b, $c, $d, $e, $f, $g, $h, $i, $j, $k, $l, $m, $n,
512+
$o, $p,
513513
],
514514
)
515515
};
@@ -535,16 +535,16 @@ pub unsafe fn _mm256_blend_epi16(
535535
$f2, 14, 15
536536
),
537537
0b01 => blend4!(
538-
$a, $b, $c, $d, $e, $f, 22, 7, $a2, $b2, $c2, $d2,
539-
$e2, $f2, 30, 15
538+
$a, $b, $c, $d, $e, $f, 22, 7, $a2, $b2, $c2, $d2, $e2,
539+
$f2, 30, 15
540540
),
541541
0b10 => blend4!(
542-
$a, $b, $c, $d, $e, $f, 6, 23, $a2, $b2, $c2, $d2,
543-
$e2, $f2, 14, 31
542+
$a, $b, $c, $d, $e, $f, 6, 23, $a2, $b2, $c2, $d2, $e2,
543+
$f2, 14, 31
544544
),
545545
_ => blend4!(
546-
$a, $b, $c, $d, $e, $f, 22, 23, $a2, $b2, $c2, $d2,
547-
$e2, $f2, 30, 31
546+
$a, $b, $c, $d, $e, $f, 22, 23, $a2, $b2, $c2, $d2, $e2,
547+
$f2, 30, 31
548548
),
549549
}
550550
};
@@ -561,18 +561,18 @@ pub unsafe fn _mm256_blend_epi16(
561561
$d2:expr
562562
) => {
563563
match (imm8 >> 4) & 0b11 {
564-
0b00 => blend3!(
565-
$a, $b, $c, $d, 4, 5, $a2, $b2, $c2, $d2, 12, 13
566-
),
567-
0b01 => blend3!(
568-
$a, $b, $c, $d, 20, 5, $a2, $b2, $c2, $d2, 28, 13
569-
),
570-
0b10 => blend3!(
571-
$a, $b, $c, $d, 4, 21, $a2, $b2, $c2, $d2, 12, 29
572-
),
573-
_ => blend3!(
574-
$a, $b, $c, $d, 20, 21, $a2, $b2, $c2, $d2, 28, 29
575-
),
564+
0b00 => {
565+
blend3!($a, $b, $c, $d, 4, 5, $a2, $b2, $c2, $d2, 12, 13)
566+
}
567+
0b01 => {
568+
blend3!($a, $b, $c, $d, 20, 5, $a2, $b2, $c2, $d2, 28, 13)
569+
}
570+
0b10 => {
571+
blend3!($a, $b, $c, $d, 4, 21, $a2, $b2, $c2, $d2, 12, 29)
572+
}
573+
_ => {
574+
blend3!($a, $b, $c, $d, 20, 21, $a2, $b2, $c2, $d2, 28, 29)
575+
}
576576
}
577577
};
578578
}
@@ -1030,8 +1030,10 @@ pub unsafe fn _mm256_cvtepu8_epi64(a: __m128i) -> __m256i {
10301030
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_extracti128_si256)
10311031
#[inline]
10321032
#[target_feature(enable = "avx2")]
1033-
#[cfg_attr(all(test, not(target_os = "windows")),
1034-
assert_instr(vextractf128, imm8 = 1))]
1033+
#[cfg_attr(
1034+
all(test, not(target_os = "windows")),
1035+
assert_instr(vextractf128, imm8 = 1)
1036+
)]
10351037
#[rustc_args_required_const(1)]
10361038
#[stable(feature = "simd_x86", since = "1.27.0")]
10371039
pub unsafe fn _mm256_extracti128_si256(a: __m256i, imm8: i32) -> __m128i {
@@ -1946,8 +1948,10 @@ pub unsafe fn _mm256_mask_i64gather_pd(
19461948
/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_inserti128_si256)
19471949
#[inline]
19481950
#[target_feature(enable = "avx2")]
1949-
#[cfg_attr(all(test, not(target_os = "windows")),
1950-
assert_instr(vinsertf128, imm8 = 1))]
1951+
#[cfg_attr(
1952+
all(test, not(target_os = "windows")),
1953+
assert_instr(vinsertf128, imm8 = 1)
1954+
)]
19511955
#[rustc_args_required_const(2)]
19521956
#[stable(feature = "simd_x86", since = "1.27.0")]
19531957
pub unsafe fn _mm256_inserti128_si256(
@@ -2783,11 +2787,11 @@ pub unsafe fn _mm256_shufflehi_epi16(a: __m256i, imm8: i32) -> __m256i {
27832787
macro_rules! shuffle_done {
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($x01:expr, $x23:expr, $x45:expr, $x67:expr) => {
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#[cfg_attr(rustfmt, rustfmt_skip)]
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simd_shuffle16(a, a, [
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0, 1, 2, 3, 4+$x01, 4+$x23, 4+$x45, 4+$x67,
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8, 9, 10, 11, 12+$x01, 12+$x23, 12+$x45, 12+$x67
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]);
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}
2790+
simd_shuffle16(a, a, [
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0, 1, 2, 3, 4+$x01, 4+$x23, 4+$x45, 4+$x67,
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8, 9, 10, 11, 12+$x01, 12+$x23, 12+$x45, 12+$x67
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]);
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};
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}
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macro_rules! shuffle_x67 {
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($x01:expr, $x23:expr, $x45:expr) => {

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