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Do not implement x86 SIMD abs with host integers
1 parent b3b1b49 commit b261535

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+10
-4
lines changed
  • src/tools/miri/src/shims/x86

1 file changed

+10
-4
lines changed

src/tools/miri/src/shims/x86/mod.rs

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -739,14 +739,20 @@ fn int_abs<'tcx>(
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740740
assert_eq!(op_len, dest_len);
741741

742+
let zero = ImmTy::from_int(0, op.layout.field(this, 0));
743+
742744
for i in 0..dest_len {
743-
let op = this.read_scalar(&this.project_index(&op, i)?)?;
745+
let op = this.read_immediate(&this.project_index(&op, i)?)?;
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let dest = this.project_index(&dest, i)?;
745747

746-
// Converting to a host "i128" works since the input is always signed.
747-
let res = op.to_int(dest.layout.size)?.unsigned_abs();
748+
let lt_zero = this.wrapping_binary_op(mir::BinOp::Lt, &op, &zero)?;
749+
let res = if lt_zero.to_scalar().to_bool()? {
750+
this.wrapping_unary_op(mir::UnOp::Neg, &op)?
751+
} else {
752+
op
753+
};
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749-
this.write_scalar(Scalar::from_uint(res, dest.layout.size), &dest)?;
755+
this.write_immediate(*res, &dest)?;
750756
}
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752758
Ok(())

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