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Merge codegen of several simd intrinsics
This reduces code duplication
1 parent c1d699d commit 5a3cfb2

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+16
-41
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1 file changed

+16
-41
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src/intrinsics/simd.rs

Lines changed: 16 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -280,7 +280,8 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
280280
});
281281
};
282282

283-
simd_add | simd_sub | simd_mul | simd_div, (c x, c y) {
283+
simd_add | simd_sub | simd_mul | simd_div | simd_rem
284+
| simd_shl | simd_shr | simd_and | simd_or | simd_xor, (c x, c y) {
284285
if !x.layout().ty.is_simd() {
285286
report_simd_type_validation_error(fx, intrinsic, span, x.layout().ty);
286287
return;
@@ -295,57 +296,31 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
295296
(ty::Uint(_), sym::simd_sub) => fx.bcx.ins().isub(x_lane, y_lane),
296297
(ty::Uint(_), sym::simd_mul) => fx.bcx.ins().imul(x_lane, y_lane),
297298
(ty::Uint(_), sym::simd_div) => fx.bcx.ins().udiv(x_lane, y_lane),
299+
(ty::Uint(_), sym::simd_rem) => fx.bcx.ins().urem(x_lane, y_lane),
298300

299301
(ty::Int(_), sym::simd_add) => fx.bcx.ins().iadd(x_lane, y_lane),
300302
(ty::Int(_), sym::simd_sub) => fx.bcx.ins().isub(x_lane, y_lane),
301303
(ty::Int(_), sym::simd_mul) => fx.bcx.ins().imul(x_lane, y_lane),
302304
(ty::Int(_), sym::simd_div) => fx.bcx.ins().sdiv(x_lane, y_lane),
305+
(ty::Int(_), sym::simd_rem) => fx.bcx.ins().srem(x_lane, y_lane),
303306

304307
(ty::Float(_), sym::simd_add) => fx.bcx.ins().fadd(x_lane, y_lane),
305308
(ty::Float(_), sym::simd_sub) => fx.bcx.ins().fsub(x_lane, y_lane),
306309
(ty::Float(_), sym::simd_mul) => fx.bcx.ins().fmul(x_lane, y_lane),
307310
(ty::Float(_), sym::simd_div) => fx.bcx.ins().fdiv(x_lane, y_lane),
311+
(ty::Float(FloatTy::F32), sym::simd_rem) => fx.lib_call(
312+
"fmodf",
313+
vec![AbiParam::new(types::F32), AbiParam::new(types::F32)],
314+
vec![AbiParam::new(types::F32)],
315+
&[x_lane, y_lane],
316+
)[0],
317+
(ty::Float(FloatTy::F64), sym::simd_rem) => fx.lib_call(
318+
"fmod",
319+
vec![AbiParam::new(types::F64), AbiParam::new(types::F64)],
320+
vec![AbiParam::new(types::F64)],
321+
&[x_lane, y_lane],
322+
)[0],
308323

309-
_ => unreachable!(),
310-
});
311-
};
312-
simd_rem, (c x, c y) {
313-
if !x.layout().ty.is_simd() {
314-
report_simd_type_validation_error(fx, intrinsic, span, x.layout().ty);
315-
return;
316-
}
317-
318-
simd_pair_for_each_lane(fx, x, y, ret, &|fx, lane_ty, _ret_lane_ty, x_lane, y_lane| {
319-
match lane_ty.kind() {
320-
ty::Uint(_) => fx.bcx.ins().urem(x_lane, y_lane),
321-
ty::Int(_) => fx.bcx.ins().srem(x_lane, y_lane),
322-
ty::Float(FloatTy::F32) => fx.lib_call(
323-
"fmodf",
324-
vec![AbiParam::new(types::F32), AbiParam::new(types::F32)],
325-
vec![AbiParam::new(types::F32)],
326-
&[x_lane, y_lane],
327-
)[0],
328-
ty::Float(FloatTy::F64) => fx.lib_call(
329-
"fmod",
330-
vec![AbiParam::new(types::F64), AbiParam::new(types::F64)],
331-
vec![AbiParam::new(types::F64)],
332-
&[x_lane, y_lane],
333-
)[0],
334-
_ => unreachable!("{:?}", lane_ty),
335-
}
336-
});
337-
};
338-
simd_shl | simd_shr | simd_and | simd_or | simd_xor, (c x, c y) {
339-
if !x.layout().ty.is_simd() {
340-
report_simd_type_validation_error(fx, intrinsic, span, x.layout().ty);
341-
return;
342-
}
343-
344-
// FIXME use vector instructions when possible
345-
simd_pair_for_each_lane(fx, x, y, ret, &|fx, lane_ty, _ret_lane_ty, x_lane, y_lane| match (
346-
lane_ty.kind(),
347-
intrinsic,
348-
) {
349324
(ty::Uint(_), sym::simd_shl) => fx.bcx.ins().ishl(x_lane, y_lane),
350325
(ty::Uint(_), sym::simd_shr) => fx.bcx.ins().ushr(x_lane, y_lane),
351326
(ty::Uint(_), sym::simd_and) => fx.bcx.ins().band(x_lane, y_lane),

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