@@ -280,7 +280,8 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
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} ) ;
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} ;
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- simd_add | simd_sub | simd_mul | simd_div, ( c x, c y) {
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+ simd_add | simd_sub | simd_mul | simd_div | simd_rem
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+ | simd_shl | simd_shr | simd_and | simd_or | simd_xor, ( c x, c y) {
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if !x. layout( ) . ty. is_simd( ) {
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report_simd_type_validation_error( fx, intrinsic, span, x. layout( ) . ty) ;
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return ;
@@ -295,57 +296,31 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
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( ty:: Uint ( _) , sym:: simd_sub) => fx. bcx. ins( ) . isub( x_lane, y_lane) ,
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( ty:: Uint ( _) , sym:: simd_mul) => fx. bcx. ins( ) . imul( x_lane, y_lane) ,
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( ty:: Uint ( _) , sym:: simd_div) => fx. bcx. ins( ) . udiv( x_lane, y_lane) ,
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+ ( ty:: Uint ( _) , sym:: simd_rem) => fx. bcx. ins( ) . urem( x_lane, y_lane) ,
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( ty:: Int ( _) , sym:: simd_add) => fx. bcx. ins( ) . iadd( x_lane, y_lane) ,
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( ty:: Int ( _) , sym:: simd_sub) => fx. bcx. ins( ) . isub( x_lane, y_lane) ,
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( ty:: Int ( _) , sym:: simd_mul) => fx. bcx. ins( ) . imul( x_lane, y_lane) ,
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( ty:: Int ( _) , sym:: simd_div) => fx. bcx. ins( ) . sdiv( x_lane, y_lane) ,
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+ ( ty:: Int ( _) , sym:: simd_rem) => fx. bcx. ins( ) . srem( x_lane, y_lane) ,
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( ty:: Float ( _) , sym:: simd_add) => fx. bcx. ins( ) . fadd( x_lane, y_lane) ,
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( ty:: Float ( _) , sym:: simd_sub) => fx. bcx. ins( ) . fsub( x_lane, y_lane) ,
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( ty:: Float ( _) , sym:: simd_mul) => fx. bcx. ins( ) . fmul( x_lane, y_lane) ,
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( ty:: Float ( _) , sym:: simd_div) => fx. bcx. ins( ) . fdiv( x_lane, y_lane) ,
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+ ( ty:: Float ( FloatTy :: F32 ) , sym:: simd_rem) => fx. lib_call(
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+ "fmodf" ,
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+ vec![ AbiParam :: new( types:: F32 ) , AbiParam :: new( types:: F32 ) ] ,
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+ vec![ AbiParam :: new( types:: F32 ) ] ,
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+ & [ x_lane, y_lane] ,
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+ ) [ 0 ] ,
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+ ( ty:: Float ( FloatTy :: F64 ) , sym:: simd_rem) => fx. lib_call(
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+ "fmod" ,
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+ vec![ AbiParam :: new( types:: F64 ) , AbiParam :: new( types:: F64 ) ] ,
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+ vec![ AbiParam :: new( types:: F64 ) ] ,
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+ & [ x_lane, y_lane] ,
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+ ) [ 0 ] ,
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- _ => unreachable!( ) ,
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- } ) ;
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- } ;
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- simd_rem, ( c x, c y) {
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- if !x. layout( ) . ty. is_simd( ) {
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- report_simd_type_validation_error( fx, intrinsic, span, x. layout( ) . ty) ;
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- return ;
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- }
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-
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- simd_pair_for_each_lane( fx, x, y, ret, & |fx, lane_ty, _ret_lane_ty, x_lane, y_lane| {
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- match lane_ty. kind( ) {
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- ty:: Uint ( _) => fx. bcx. ins( ) . urem( x_lane, y_lane) ,
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- ty:: Int ( _) => fx. bcx. ins( ) . srem( x_lane, y_lane) ,
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- ty:: Float ( FloatTy :: F32 ) => fx. lib_call(
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- "fmodf" ,
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- vec![ AbiParam :: new( types:: F32 ) , AbiParam :: new( types:: F32 ) ] ,
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- vec![ AbiParam :: new( types:: F32 ) ] ,
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- & [ x_lane, y_lane] ,
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- ) [ 0 ] ,
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- ty:: Float ( FloatTy :: F64 ) => fx. lib_call(
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- "fmod" ,
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- vec![ AbiParam :: new( types:: F64 ) , AbiParam :: new( types:: F64 ) ] ,
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- vec![ AbiParam :: new( types:: F64 ) ] ,
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- & [ x_lane, y_lane] ,
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- ) [ 0 ] ,
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- _ => unreachable!( "{:?}" , lane_ty) ,
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- }
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- } ) ;
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- } ;
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- simd_shl | simd_shr | simd_and | simd_or | simd_xor, ( c x, c y) {
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- if !x. layout( ) . ty. is_simd( ) {
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- report_simd_type_validation_error( fx, intrinsic, span, x. layout( ) . ty) ;
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- return ;
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- }
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-
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- // FIXME use vector instructions when possible
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- simd_pair_for_each_lane( fx, x, y, ret, & |fx, lane_ty, _ret_lane_ty, x_lane, y_lane| match (
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- lane_ty. kind( ) ,
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- intrinsic,
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- ) {
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( ty:: Uint ( _) , sym:: simd_shl) => fx. bcx. ins( ) . ishl( x_lane, y_lane) ,
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( ty:: Uint ( _) , sym:: simd_shr) => fx. bcx. ins( ) . ushr( x_lane, y_lane) ,
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( ty:: Uint ( _) , sym:: simd_and) => fx. bcx. ins( ) . band( x_lane, y_lane) ,
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