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Make FalseEdges always have two targets
We never have more than one imaginary target, so we have no reason for a `Vec`
1 parent f492693 commit 2f5807c

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7 files changed

+21
-32
lines changed

7 files changed

+21
-32
lines changed

src/librustc/mir/mod.rs

Lines changed: 9 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1185,9 +1185,9 @@ pub enum TerminatorKind<'tcx> {
11851185
FalseEdges {
11861186
/// The target normal control flow will take
11871187
real_target: BasicBlock,
1188-
/// The list of blocks control flow could conceptually take, but won't
1188+
/// A block control flow could conceptually take, but won't
11891189
/// in practice
1190-
imaginary_targets: Vec<BasicBlock>,
1190+
imaginary_target: BasicBlock,
11911191
},
11921192
/// A terminator for blocks that only take one path in reality, but where we
11931193
/// reserve the right to unwind in borrowck, even if it won't happen in practice.
@@ -1324,8 +1324,8 @@ impl<'tcx> TerminatorKind<'tcx> {
13241324
SwitchInt { ref targets, .. } => None.into_iter().chain(&targets[..]),
13251325
FalseEdges {
13261326
ref real_target,
1327-
ref imaginary_targets,
1328-
} => Some(real_target).into_iter().chain(&imaginary_targets[..]),
1327+
ref imaginary_target,
1328+
} => Some(real_target).into_iter().chain(slice::from_ref(imaginary_target)),
13291329
}
13301330
}
13311331

@@ -1411,10 +1411,10 @@ impl<'tcx> TerminatorKind<'tcx> {
14111411
} => None.into_iter().chain(&mut targets[..]),
14121412
FalseEdges {
14131413
ref mut real_target,
1414-
ref mut imaginary_targets,
1414+
ref mut imaginary_target,
14151415
} => Some(real_target)
14161416
.into_iter()
1417-
.chain(&mut imaginary_targets[..]),
1417+
.chain(slice::from_mut(imaginary_target)),
14181418
}
14191419
}
14201420

@@ -1714,12 +1714,9 @@ impl<'tcx> TerminatorKind<'tcx> {
17141714
Assert { cleanup: None, .. } => vec!["".into()],
17151715
Assert { .. } => vec!["success".into(), "unwind".into()],
17161716
FalseEdges {
1717-
ref imaginary_targets,
17181717
..
17191718
} => {
1720-
let mut l = vec!["real".into()];
1721-
l.resize(imaginary_targets.len() + 1, "imaginary".into());
1722-
l
1719+
vec!["real".into(), "imaginary".into()]
17231720
}
17241721
FalseUnwind {
17251722
unwind: Some(_), ..
@@ -3342,10 +3339,10 @@ impl<'tcx> TypeFoldable<'tcx> for Terminator<'tcx> {
33423339
Unreachable => Unreachable,
33433340
FalseEdges {
33443341
real_target,
3345-
ref imaginary_targets,
3342+
imaginary_target,
33463343
} => FalseEdges {
33473344
real_target,
3348-
imaginary_targets: imaginary_targets.clone(),
3345+
imaginary_target,
33493346
},
33503347
FalseUnwind {
33513348
real_target,

src/librustc_mir/borrow_check/mod.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -806,7 +806,7 @@ impl<'cx, 'gcx, 'tcx> DataflowResultsConsumer<'cx, 'tcx> for MirBorrowckCtxt<'cx
806806
| TerminatorKind::Unreachable
807807
| TerminatorKind::FalseEdges {
808808
real_target: _,
809-
imaginary_targets: _,
809+
imaginary_target: _,
810810
}
811811
| TerminatorKind::FalseUnwind {
812812
real_target: _,

src/librustc_mir/borrow_check/nll/invalidation.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -244,7 +244,7 @@ impl<'cx, 'tcx, 'gcx> Visitor<'tcx> for InvalidationGenerator<'cx, 'tcx, 'gcx> {
244244
| TerminatorKind::Unreachable
245245
| TerminatorKind::FalseEdges {
246246
real_target: _,
247-
imaginary_targets: _,
247+
imaginary_target: _,
248248
}
249249
| TerminatorKind::FalseUnwind {
250250
real_target: _,

src/librustc_mir/borrow_check/nll/type_check/mod.rs

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1792,12 +1792,10 @@ impl<'a, 'gcx, 'tcx> TypeChecker<'a, 'gcx, 'tcx> {
17921792
}
17931793
TerminatorKind::FalseEdges {
17941794
real_target,
1795-
ref imaginary_targets,
1795+
imaginary_target,
17961796
} => {
17971797
self.assert_iscleanup(mir, block_data, real_target, is_cleanup);
1798-
for target in imaginary_targets {
1799-
self.assert_iscleanup(mir, block_data, *target, is_cleanup);
1800-
}
1798+
self.assert_iscleanup(mir, block_data, imaginary_target, is_cleanup);
18011799
}
18021800
TerminatorKind::FalseUnwind {
18031801
real_target,

src/librustc_mir/build/matches/mod.rs

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -963,9 +963,7 @@ impl<'a, 'gcx, 'tcx> Builder<'a, 'gcx, 'tcx> {
963963
source_info,
964964
TerminatorKind::FalseEdges {
965965
real_target: second_candidate.pre_binding_block,
966-
imaginary_targets: vec![
967-
first_candidate.next_candidate_pre_binding_block
968-
],
966+
imaginary_target: first_candidate.next_candidate_pre_binding_block,
969967
}
970968
)
971969
} else {
@@ -986,7 +984,7 @@ impl<'a, 'gcx, 'tcx> Builder<'a, 'gcx, 'tcx> {
986984
source_info,
987985
TerminatorKind::FalseEdges {
988986
real_target: unreachable,
989-
imaginary_targets: vec![candidate.next_candidate_pre_binding_block],
987+
imaginary_targets: candidate.next_candidate_pre_binding_block,
990988
}
991989
);
992990
self.cfg.terminate(unreachable, source_info, TerminatorKind::Unreachable);
@@ -1003,7 +1001,7 @@ impl<'a, 'gcx, 'tcx> Builder<'a, 'gcx, 'tcx> {
10031001
source_info,
10041002
TerminatorKind::FalseEdges {
10051003
real_target: block,
1006-
imaginary_targets: vec![last_candidate.next_candidate_pre_binding_block]
1004+
imaginary_target: last_candidate.next_candidate_pre_binding_block,
10071005
}
10081006
);
10091007
Some(block)
@@ -1332,7 +1330,7 @@ impl<'a, 'gcx, 'tcx> Builder<'a, 'gcx, 'tcx> {
13321330
candidate_source_info,
13331331
TerminatorKind::FalseEdges {
13341332
real_target: block,
1335-
imaginary_targets: vec![candidate.next_candidate_pre_binding_block],
1333+
imaginary_target: candidate.next_candidate_pre_binding_block,
13361334
},
13371335
);
13381336
self.ascribe_types(block, &candidate.ascriptions);

src/librustc_mir/dataflow/mod.rs

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -795,11 +795,9 @@ impl<'a, 'tcx: 'a, D> DataflowAnalysis<'a, 'tcx, D> where D: BitDenotation<'tcx>
795795
self.propagate_bits_into_entry_set_for(in_out, dest_bb, dirty_list);
796796
}
797797
}
798-
mir::TerminatorKind::FalseEdges { real_target, ref imaginary_targets } => {
798+
mir::TerminatorKind::FalseEdges { real_target, imaginary_target } => {
799799
self.propagate_bits_into_entry_set_for(in_out, real_target, dirty_list);
800-
for target in imaginary_targets {
801-
self.propagate_bits_into_entry_set_for(in_out, *target, dirty_list);
802-
}
800+
self.propagate_bits_into_entry_set_for(in_out, imaginary_target, dirty_list);
803801
}
804802
mir::TerminatorKind::FalseUnwind { real_target, unwind } => {
805803
self.propagate_bits_into_entry_set_for(in_out, real_target, dirty_list);

src/librustc_mir/transform/inline.rs

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -784,11 +784,9 @@ impl<'a, 'tcx> MutVisitor<'tcx> for Integrator<'a, 'tcx> {
784784
}
785785
TerminatorKind::Abort => { }
786786
TerminatorKind::Unreachable => { }
787-
TerminatorKind::FalseEdges { ref mut real_target, ref mut imaginary_targets } => {
787+
TerminatorKind::FalseEdges { ref mut real_target, ref mut imaginary_target } => {
788788
*real_target = self.update_target(*real_target);
789-
for target in imaginary_targets {
790-
*target = self.update_target(*target);
791-
}
789+
*imaginary_target = self.update_target(*imaginary_target);
792790
}
793791
TerminatorKind::FalseUnwind { real_target: _ , unwind: _ } =>
794792
// see the ordering of passes in the optimized_mir query.

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