Auto merge of #110713 - cjgillot:track-mir-opt, r=scottmcm

Add mir-opt tests to track MIR quality.

cc `@scottmcm` `@saethlin`

If you have other ideas, please say so.

Author: bors

tests/mir-opt/instcombine_duplicate_switch_targets_e2e.ub_if_b.PreCodegen.after.mir

@@ -0,0 +1,3 @@
+The goal of this directory is to track the quality of MIR that is given to codegen in a standard `-O` condiguration.
+
+As such, feel free to `--bless` whatever changes you get here, so long as doing so doesn't add substantially more MIR.

tests/mir-opt/lower_intrinsics_e2e.f_u64.PreCodegen.after.mir

@@ -1,13 +1,14 @@
-// compile-flags: -Zmir-opt-level=2 -Zinline-mir
+// compile-flags: -O -Zmir-opt-level=2 -Cdebuginfo=0
 // ignore-debug: standard library debug assertions add a panic that breaks this optimization
+
 #![crate_type = "lib"]
 
 pub enum Thing {
     A,
     B,
 }
 
-// EMIT_MIR instcombine_duplicate_switch_targets_e2e.ub_if_b.PreCodegen.after.mir
+// EMIT_MIR duplicate_switch_targets.ub_if_b.PreCodegen.after.mir
 pub unsafe fn ub_if_b(t: Thing) -> Thing {
     match t {
         Thing::A => t,

tests/mir-opt/lower_intrinsics_e2e.f_unit.PreCodegen.after.mir

@@ -0,0 +1,27 @@
+// MIR for `ub_if_b` after PreCodegen
+
+fn ub_if_b(_1: Thing) -> Thing {
+    debug t => _1;                       // in scope 0 at $DIR/duplicate_switch_targets.rs:+0:23: +0:24
+    let mut _0: Thing;                   // return place in scope 0 at $DIR/duplicate_switch_targets.rs:+0:36: +0:41
+    let mut _2: isize;                   // in scope 0 at $DIR/duplicate_switch_targets.rs:+2:9: +2:17
+    scope 1 (inlined unreachable_unchecked) { // at $DIR/duplicate_switch_targets.rs:15:21: 15:55
+        scope 2 {
+            scope 3 (inlined unreachable_unchecked::runtime) { // at $SRC_DIR/core/src/intrinsics.rs:LL:COL
+            }
+        }
+    }
+
+    bb0: {
+        _2 = discriminant(_1);           // scope 0 at $DIR/duplicate_switch_targets.rs:+1:11: +1:12
+        switchInt(move _2) -> [0: bb2, otherwise: bb1]; // scope 0 at $DIR/duplicate_switch_targets.rs:+1:5: +1:12
+    }
+
+    bb1: {
+        unreachable;                     // scope 2 at $SRC_DIR/core/src/intrinsics.rs:LL:COL
+    }
+
+    bb2: {
+        _0 = move _1;                    // scope 0 at $DIR/duplicate_switch_targets.rs:+2:21: +2:22
+        return;                          // scope 0 at $DIR/duplicate_switch_targets.rs:+5:2: +5:2
+    }
+}

tests/mir-opt/pre-codegen/README.md

@@ -0,0 +1,26 @@
+// MIR for `f_u64` after PreCodegen
+
+fn f_u64() -> () {
+    let mut _0: ();                      // return place in scope 0 at $DIR/intrinsics.rs:+0:16: +0:16
+    let mut _1: u64;                     // in scope 0 at $DIR/intrinsics.rs:+1:5: +1:21
+    scope 1 (inlined f_dispatch::<u64>) { // at $DIR/intrinsics.rs:19:5: 19:21
+        debug t => const 0_u64;          // in scope 1 at $DIR/intrinsics.rs:23:22: 23:23
+        let _2: ();                      // in scope 1 at $DIR/intrinsics.rs:27:9: 27:21
+        scope 2 (inlined std::mem::size_of::<u64>) { // at $DIR/intrinsics.rs:24:8: 24:32
+        }
+    }
+
+    bb0: {
+        StorageLive(_1);                 // scope 0 at $DIR/intrinsics.rs:+1:5: +1:21
+        _1 = const 0_u64;                // scope 0 at $DIR/intrinsics.rs:+1:5: +1:21
+        _2 = f_non_zst::<u64>(move _1) -> [return: bb1, unwind unreachable]; // scope 1 at $DIR/intrinsics.rs:27:9: 27:21
+                                         // mir::Constant
+                                         // + span: $DIR/intrinsics.rs:27:9: 27:18
+                                         // + literal: Const { ty: fn(u64) {f_non_zst::<u64>}, val: Value(<ZST>) }
+    }
+
+    bb1: {
+        StorageDead(_1);                 // scope 0 at $DIR/intrinsics.rs:+1:5: +1:21
+        return;                          // scope 0 at $DIR/intrinsics.rs:+2:2: +2:2
+    }
+}

tests/mir-opt/instcombine_duplicate_switch_targets_e2e.rs renamed to tests/mir-opt/pre-codegen/duplicate_switch_targets.rs

@@ -0,0 +1,22 @@
+// MIR for `f_unit` after PreCodegen
+
+fn f_unit() -> () {
+    let mut _0: ();                      // return place in scope 0 at $DIR/intrinsics.rs:+0:17: +0:17
+    scope 1 (inlined f_dispatch::<()>) { // at $DIR/intrinsics.rs:13:5: 13:19
+        debug t => const ();             // in scope 1 at $DIR/intrinsics.rs:23:22: 23:23
+        let _1: ();                      // in scope 1 at $DIR/intrinsics.rs:25:9: 25:17
+        scope 2 (inlined std::mem::size_of::<()>) { // at $DIR/intrinsics.rs:24:8: 24:32
+        }
+    }
+
+    bb0: {
+        _1 = f_zst::<()>(const ()) -> [return: bb1, unwind unreachable]; // scope 1 at $DIR/intrinsics.rs:25:9: 25:17
+                                         // mir::Constant
+                                         // + span: $DIR/intrinsics.rs:25:9: 25:14
+                                         // + literal: Const { ty: fn(()) {f_zst::<()>}, val: Value(<ZST>) }
+    }
+
+    bb1: {
+        return;                          // scope 0 at $DIR/intrinsics.rs:+2:2: +2:2
+    }
+}

tests/mir-opt/pre-codegen/duplicate_switch_targets.ub_if_b.PreCodegen.after.mir

@@ -1,16 +1,20 @@
+// compile-flags: -O -C debuginfo=0 -Zmir-opt-level=2
+// only-64bit
+// ignore-debug
+
 // Checks that we do not have any branches in the MIR for the two tested functions.
 
 // compile-flags: -Cpanic=abort
 #![feature(core_intrinsics)]
 #![crate_type = "lib"]
 
-// EMIT_MIR lower_intrinsics_e2e.f_unit.PreCodegen.after.mir
+// EMIT_MIR intrinsics.f_unit.PreCodegen.after.mir
 pub fn f_unit() {
     f_dispatch(());
 }
 
 
-// EMIT_MIR lower_intrinsics_e2e.f_u64.PreCodegen.after.mir
+// EMIT_MIR intrinsics.f_u64.PreCodegen.after.mir
 pub fn f_u64() {
     f_dispatch(0u64);
 }