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lines changed Original file line number Diff line number Diff line change 27
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//! from acquire/release operations. If weak memory orderings are explored then this
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//! may need to change or be updated accordingly.
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//!
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+ //! Per the C++ spec for the memory model a sequentially consistent operation:
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+ //! "A load operation with this memory order performs an acquire operation,
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+ //! a store performs a release operation, and read-modify-write performs
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+ //! both an acquire operation and a release operation, plus a single total
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+ //! order exists in which all threads observe all modifications in the same
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+ //! order (see Sequentially-consistent ordering below) "
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+ //! So in the absence of weak memory effects a seq-cst load & a seq-cst store is identical
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+ //! to a acquire load and a release store given the global sequentially consistent order
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+ //! of the schedule.
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+ //!
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//! FIXME:
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//! currently we have our own local copy of the currently active thread index and names, this is due
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//! in part to the inability to access the current location of threads.active_thread inside the AllocExtra
@@ -196,6 +206,7 @@ struct MemoryCellClocks {
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/// The vector-clock of the timestamp of the last read operation
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/// performed by a thread since the last write operation occured.
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+ /// It is reset to zero on each write operation.
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read : VClock ,
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/// Atomic acquire & release sequence tracking clocks.
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+ // ignore-windows: Concurrency on Windows is not supported yet.
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+ // compile-flags: -Zmiri-disable-data-race-detector
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+
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+ use std:: thread:: spawn;
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+
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+ #[ derive( Copy , Clone ) ]
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+ struct EvilSend < T > ( pub T ) ;
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+
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+ unsafe impl < T > Send for EvilSend < T > { }
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+ unsafe impl < T > Sync for EvilSend < T > { }
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+
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+ pub fn main ( ) {
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+ let mut a = 0u32 ;
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+ let b = & mut a as * mut u32 ;
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+ let c = EvilSend ( b) ;
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+ unsafe {
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+ let j1 = spawn ( move || {
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+ * c. 0 = 32 ;
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+ } ) ;
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+
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+ let j2 = spawn ( move || {
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+ * c. 0 = 64 ; //~ ERROR Data race
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+ } ) ;
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+
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+ j1. join ( ) . unwrap ( ) ;
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+ j2. join ( ) . unwrap ( ) ;
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+ }
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+ }
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+ warning: thread support is experimental, no weak memory effects are currently emulated.
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+
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