adapt to modified rustc, all tests pass (with rustc changes)

Author: nia-e

src/alloc_addresses/mod.rs

@@ -468,53 +468,36 @@ pub trait EvalContextExt<'tcx>: crate::MiriInterpCxExt<'tcx> {
     /// This overapproximates the modifications which external code might make to memory:
     /// We set all reachable allocations as initialized, mark all reachable provenances as exposed
     /// and overwrite them with `Provenance::WILDCARD`.
-    fn prepare_exposed_for_native_call(&mut self) -> InterpResult<'tcx> {
+    fn prepare_exposed_for_native_call(&mut self, paranoid: bool) -> InterpResult<'tcx> {
         let this = self.eval_context_mut();
         // We need to make a deep copy of this list, but it's fine; it also serves as scratch space
         // for the search within `prepare_for_native_call`.
         let exposed: Vec<AllocId> =
             this.machine.alloc_addresses.get_mut().exposed.iter().copied().collect();
-        this.prepare_for_native_call(exposed)
+        this.prepare_for_native_call(exposed, paranoid)
     }
 
-    /// Similar to `prepare_exposed_for_native_call`, but makes use of information obtained about
-    /// memory accesses during FFI to determine which provenances should be exposed and which
-    /// new allocations were created and possibly exposed.
+    /// Makes use of information obtained about memory accesses during FFI to determine which
+    /// provenances should be exposed. Note that if `prepare_exposed_for_native_call` was not
+    /// called before the FFI (with `paranoid` set to false) then some of the writes may be
+    /// lost!
     fn apply_events(&mut self, events: crate::shims::trace::MemEvents) -> InterpResult<'tcx> {
         let this = self.eval_context_mut();
-        //let accesses = events.accesses;
-        /*let handle = this.machine.alloc_addresses.borrow();
-        for id in &handle.exposed {
-            let &base_addr = handle.base_addr.get(id).unwrap();
-            let info = this.get_alloc_info(*id);
-
-            //let found = vec![];
-            for (acc_base, acc_len, acc_kind) in &events.accesses {
-                // If ranges overlap
-                if *acc_base <= base_addr.strict_add(info.size.bytes())
-                    && base_addr <= acc_base.strict_add(*acc_len)
-                {
-                    if info.mutbl.is_not() && acc_kind.did_write() {
-                        throw_ub_format!(""); // TODO: fill this in lol
-                    }
-
-                    if acc_kind.did_read() {
-                        let src = Pointer::from_addr_invalid(*acc_base);
-                        this.read_immediate_raw(&src);
-                        self.expose_provenance(provenance)
-                    }
-
-                    if acc_kind.did_write() {
-                        //let alloc = self.alloc_id_from_addr(addr, size, only_exposed_allocations)
-                    }
-                }
-            }
-        }*/
-        /*for (acc_base, acc_len, acc_kind) in &events.accesses {
-            let alloc_id = self.alloc_id_from_addr(addr, size, only_exposed_allocations)
-        }*/
+        let exposed: Vec<AllocId> =  this.machine.alloc_addresses.get_mut().exposed.iter().copied().collect();
+        let accesses = events.accesses.into_iter().map(|(range, kind)| {
+            // Can't get around this without pulling in serde as a dependency of rustc, because
+            // the MemEvents need to be sent over IPC, or manually implementing serialisation/
+            // deserialisation for it, which is a lot of extra code for little gain
+            let kind = match kind {
+                k if k == 0 => ForeignAccessKind::Read,
+                k if k == 1 => ForeignAccessKind::Write,
+                k if k == 2 => ForeignAccessKind::ReadWrite,
+                _ => unreachable!(),
+            };
+            (range, kind)
+        }).collect();
 
-        interp_ok(())
+        this.apply_accesses(exposed, accesses)
     }
 }
 

src/lib.rs

@@ -54,7 +54,7 @@ extern crate tracing;
 extern crate rustc_abi;
 extern crate rustc_apfloat;
 extern crate rustc_ast;
-extern crate rustc_attr_parsing;
+extern crate rustc_attr_data_structures;
 extern crate rustc_const_eval;
 extern crate rustc_data_structures;
 extern crate rustc_errors;

src/machine.rs

@@ -13,7 +13,7 @@ use rand::rngs::StdRng;
 use rand::{Rng, SeedableRng};
 use rustc_abi::{Align, ExternAbi, Size};
 use rustc_apfloat::{Float, FloatConvert};
-use rustc_attr_parsing::InlineAttr;
+use rustc_attr_data_structures::InlineAttr;
 use rustc_data_structures::fx::{FxHashMap, FxHashSet};
 #[allow(unused)]
 use rustc_data_structures::static_assert_size;

src/shims/native_lib.rs

@@ -180,10 +180,8 @@ pub trait EvalContextExt<'tcx>: crate::MiriInterpCxExt<'tcx> {
             }
         }
 
-        if super::trace::Supervisor::init().is_err() {
-            // Worst-case prepare all exposed memory.
-            this.prepare_exposed_for_native_call()?;
-        }
+        // Prepare all exposed memory, depending on whether we have a supervisor process.
+        this.prepare_exposed_for_native_call(super::trace::Supervisor::init().is_err())?;
 
         // Convert them to `libffi::high::Arg` type.
         let libffi_args = libffi_args
@@ -194,7 +192,6 @@ pub trait EvalContextExt<'tcx>: crate::MiriInterpCxExt<'tcx> {
         // Call the function and store output, depending on return type in the function signature.
         let ret = this.call_native_with_args(link_name, dest, code_ptr, libffi_args)?;
         if let Some(events) = super::trace::Supervisor::get_events() {
-            eprintln!("accesses: {events:#018x?}");
             this.apply_events(events)?;
         }
         this.write_immediate(*ret, dest)?;
@@ -206,13 +203,12 @@ pub trait EvalContextExt<'tcx>: crate::MiriInterpCxExt<'tcx> {
 unsafe fn do_native_call<T: libffi::high::CType>(ptr: CodePtr, args: &[ffi::Arg<'_>]) -> T {
     use shims::trace::Supervisor;
 
-    let ret = unsafe {
+    unsafe {
         Supervisor::start_ffi();
         let ret = ffi::call(ptr, args);
         Supervisor::end_ffi();
         ret
-    };
-    ret
+    }
 }
 
 #[cfg(not(all(unix, any(target_arch = "x86", target_arch = "x86_64"))))]

src/shims/trace.rs

@@ -1,6 +1,9 @@
+use std::ops::Range;
+
 use ipc_channel::ipc;
 use nix::sys::{ptrace, signal, wait};
 use nix::unistd;
+use rustc_const_eval::interpret::ForeignAccessKind;
 
 use crate::discrete_alloc;
 use crate::helpers::ToU64;
@@ -186,45 +189,28 @@ pub enum TraceRequest {
 
 #[derive(serde::Serialize, serde::Deserialize, Debug)]
 pub struct MemEvents {
-    pub accesses: Vec<(u64, u64, MemAccessType)>,
-    pub mappings: Vec<(u64, u64)>,
+    pub accesses: Vec<(Range<u64>, i32)>,
+    pub mappings: Vec<Range<u64>>,
 }
 
-#[derive(serde::Serialize, serde::Deserialize, Debug, Clone)]
-pub enum MemAccessType {
-    Read,
-    Write,
-    ReadWrite,
+trait UpdateAcc {
+    fn update(&mut self, other: ForeignAccessKind);
 }
 
-impl MemAccessType {
-    fn update(&mut self, other: MemAccessType) {
+impl UpdateAcc for ForeignAccessKind {
+    fn update(&mut self, other: ForeignAccessKind) {
         match self {
-            MemAccessType::Read =>
+            ForeignAccessKind::Read =>
                 match other {
-                    MemAccessType::Read => (),
-                    _ => *self = MemAccessType::ReadWrite,
+                    ForeignAccessKind::Read => (),
+                    _ => *self = ForeignAccessKind::ReadWrite,
                 },
-            MemAccessType::Write =>
+            ForeignAccessKind::Write =>
                 match other {
-                    MemAccessType::Write => (),
-                    _ => *self = MemAccessType::ReadWrite,
+                    ForeignAccessKind::Write => (),
+                    _ => *self = ForeignAccessKind::ReadWrite,
                 },
-            MemAccessType::ReadWrite => (),
-        }
-    }
-
-    pub fn did_read(&self) -> bool {
-        match self {
-            MemAccessType::Write => false,
-            _ => true,
-        }
-    }
-
-    pub fn did_write(&self) -> bool {
-        match self {
-            MemAccessType::Read => false,
-            _ => true,
+            ForeignAccessKind::ReadWrite => (),
         }
     }
 }
@@ -284,7 +270,7 @@ impl Iterator for ChildListener {
 /// created before the fork are the same).
 fn sv_loop(listener: ChildListener, t_event: ipc::IpcSender<MemEvents>) -> ! {
     // Things that we return to the child process
-    let mut accesses: Vec<(u64, u64, MemAccessType)> = vec![];
+    let mut accesses: Vec<(u64, u64, ForeignAccessKind)> = vec![];
     let mut mappings: Vec<(u64, u64)> = vec![];
 
     // Memory allocated on the MiriMachine
@@ -422,7 +408,12 @@ fn sv_loop(listener: ChildListener, t_event: ipc::IpcSender<MemEvents>) -> ! {
 
                     TraceRequest::EndFfi => {
                         signal::kill(main_pid, signal::SIGSTOP).unwrap();
-                        t_event.send(MemEvents { accesses, mappings }).unwrap();
+                        t_event.send(MemEvents {
+                            accesses: accesses.into_iter().map(|(addr, len, kind)| {
+                                (addr..addr+len, kind as i32)
+                            }).collect(),
+                            mappings: mappings.into_iter().map(|(addr, len)| (addr..addr+len)).collect(),
+                        }).unwrap();
                         accesses = vec![];
                         mappings = vec![];
                         if let Err(ret) = wait_for_signal(main_pid, signal::SIGSTOP, false) {
@@ -572,7 +563,7 @@ fn handle_munmap(
 fn handle_segfault(
     pid: unistd::Pid,
     ch_pages: &[u64],
-    accesses: &mut Vec<(u64, u64, MemAccessType)>,
+    accesses: &mut Vec<(u64, u64, ForeignAccessKind)>,
 ) -> Result<(), i32> {
     let siginfo = ptrace::getsiginfo(pid).unwrap();
     let addr = unsafe { siginfo.si_addr().addr().to_u64() };
@@ -627,14 +618,14 @@ fn handle_segfault(
         let instr = decoder.decode();
         let memsize = instr.op_code().memory_size().size().to_u64();
         let mem = fac.info(&instr).used_memory();
-        let acc = mem.iter().fold(None, |mut curr: Option<MemAccessType>, m| {
+        let acc = mem.iter().fold(None, |mut curr: Option<ForeignAccessKind>, m| {
             if let Some(m) = match m.access() {
-                iced_x86::OpAccess::Read => Some(MemAccessType::Read),
-                iced_x86::OpAccess::CondRead => Some(MemAccessType::Read),
-                iced_x86::OpAccess::Write => Some(MemAccessType::Write),
-                iced_x86::OpAccess::CondWrite => Some(MemAccessType::Write),
-                iced_x86::OpAccess::ReadWrite => Some(MemAccessType::ReadWrite),
-                iced_x86::OpAccess::ReadCondWrite => Some(MemAccessType::ReadWrite),
+                iced_x86::OpAccess::Read => Some(ForeignAccessKind::Read),
+                iced_x86::OpAccess::CondRead => Some(ForeignAccessKind::Read),
+                iced_x86::OpAccess::Write => Some(ForeignAccessKind::Write),
+                iced_x86::OpAccess::CondWrite => Some(ForeignAccessKind::Write),
+                iced_x86::OpAccess::ReadWrite => Some(ForeignAccessKind::ReadWrite),
+                iced_x86::OpAccess::ReadCondWrite => Some(ForeignAccessKind::ReadWrite),
                 _ => None,
             } {
                 if let Some(curr) = curr.as_mut() {