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Merging r353493:
------------------------------------------------------------------------ r353493 | efriedma | 2019-02-08 02:17:49 +0100 (Fri, 08 Feb 2019) | 9 lines [COFF, ARM64] Fix types for _ReadStatusReg, _WriteStatusReg r344765 added those intrinsics, but used the wrong types. Patch by Mike Hommey Differential Revision: https://reviews.llvm.org/D57636 ------------------------------------------------------------------------ llvm-svn: 353828
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4 files changed

+71
-50
lines changed

4 files changed

+71
-50
lines changed

‎clang/include/clang/Basic/BuiltinsAArch64.def

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -204,8 +204,8 @@ TARGET_HEADER_BUILTIN(_InterlockedDecrement64_rel, "LLiLLiD*", "nh", "intrin.h",
204204

205205
TARGET_HEADER_BUILTIN(_ReadWriteBarrier, "v", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
206206
TARGET_HEADER_BUILTIN(__getReg, "ULLii", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
207-
TARGET_HEADER_BUILTIN(_ReadStatusReg, "ii", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
208-
TARGET_HEADER_BUILTIN(_WriteStatusReg, "vii", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
207+
TARGET_HEADER_BUILTIN(_ReadStatusReg, "LLii", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
208+
TARGET_HEADER_BUILTIN(_WriteStatusReg, "viLLi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
209209
TARGET_HEADER_BUILTIN(_AddressOfReturnAddress, "v*", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
210210

211211
#undef BUILTIN

‎clang/lib/CodeGen/CGBuiltin.cpp

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7052,19 +7052,16 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
70527052
llvm::Value *Metadata = llvm::MetadataAsValue::get(Context, RegName);
70537053

70547054
llvm::Type *RegisterType = Int64Ty;
7055-
llvm::Type *ValueType = Int32Ty;
70567055
llvm::Type *Types[] = { RegisterType };
70577056

70587057
if (BuiltinID == AArch64::BI_ReadStatusReg) {
70597058
llvm::Value *F = CGM.getIntrinsic(llvm::Intrinsic::read_register, Types);
7060-
llvm::Value *Call = Builder.CreateCall(F, Metadata);
70617059

7062-
return Builder.CreateTrunc(Call, ValueType);
7060+
return Builder.CreateCall(F, Metadata);
70637061
}
70647062

70657063
llvm::Value *F = CGM.getIntrinsic(llvm::Intrinsic::write_register, Types);
70667064
llvm::Value *ArgValue = EmitScalarExpr(E->getArg(1));
7067-
ArgValue = Builder.CreateZExt(ArgValue, RegisterType);
70687065

70697066
return Builder.CreateCall(F, { Metadata, ArgValue });
70707067
}

‎clang/lib/Headers/intrin.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -564,8 +564,8 @@ __nop(void) {
564564
#if defined(__aarch64__)
565565
unsigned __int64 __getReg(int);
566566
long _InterlockedAdd(long volatile *Addend, long Value);
567-
int _ReadStatusReg(int);
568-
void _WriteStatusReg(int, int);
567+
__int64 _ReadStatusReg(int);
568+
void _WriteStatusReg(int, __int64);
569569

570570
static inline unsigned short _byteswap_ushort (unsigned short val) {
571571
return __builtin_bswap16(val);

‎clang/test/CodeGen/arm64-microsoft-status-reg.cpp

Lines changed: 66 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -23,88 +23,112 @@
2323
#define ARM64_TPIDRRO_EL0 ARM64_SYSREG(3,3,13, 0,3) // Thread ID Register, User Read Only [CP15_TPIDRURO]
2424
#define ARM64_TPIDR_EL1 ARM64_SYSREG(3,0,13, 0,4) // Thread ID Register, Privileged Only [CP15_TPIDRPRW]
2525

26-
void check_ReadWriteStatusReg(int v) {
27-
int ret;
26+
// From intrin.h
27+
__int64 _ReadStatusReg(int);
28+
void _WriteStatusReg(int, __int64);
29+
30+
void check_ReadWriteStatusReg(__int64 v) {
31+
__int64 ret;
2832
ret = _ReadStatusReg(ARM64_CNTVCT);
29-
// CHECK-ASM: mrs x8, CNTVCT_EL0
30-
// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD2:.*]])
33+
// CHECK-ASM: mrs x0, CNTVCT_EL0
34+
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD2:.*]])
35+
// CHECK-IR-NEXT: store i64 %[[VAR]]
3136

3237
ret = _ReadStatusReg(ARM64_PMCCNTR_EL0);
33-
// CHECK-ASM: mrs x8, PMCCNTR_EL0
34-
// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD3:.*]])
38+
// CHECK-ASM: mrs x0, PMCCNTR_EL0
39+
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD3:.*]])
40+
// CHECK-IR-NEXT: store i64 %[[VAR]]
3541

3642
ret = _ReadStatusReg(ARM64_PMSELR_EL0);
37-
// CHECK-ASM: mrs x8, PMSELR_EL0
38-
// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD4:.*]])
43+
// CHECK-ASM: mrs x0, PMSELR_EL0
44+
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD4:.*]])
45+
// CHECK-IR-NEXT: store i64 %[[VAR]]
3946

4047
ret = _ReadStatusReg(ARM64_PMXEVCNTR_EL0);
41-
// CHECK-ASM: mrs x8, PMXEVCNTR_EL0
42-
// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD5:.*]])
48+
// CHECK-ASM: mrs x0, PMXEVCNTR_EL0
49+
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD5:.*]])
50+
// CHECK-IR-NEXT: store i64 %[[VAR]]
4351

4452
ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(0));
45-
// CHECK-ASM: mrs x8, PMEVCNTR0_EL0
46-
// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD6:.*]])
53+
// CHECK-ASM: mrs x0, PMEVCNTR0_EL0
54+
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD6:.*]])
55+
// CHECK-IR-NEXT: store i64 %[[VAR]]
4756

4857
ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(1));
49-
// CHECK-ASM: mrs x8, PMEVCNTR1_EL0
50-
// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD7:.*]])
58+
// CHECK-ASM: mrs x0, PMEVCNTR1_EL0
59+
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD7:.*]])
60+
// CHECK-IR-NEXT: store i64 %[[VAR]]
5161

5262
ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(30));
53-
// CHECK-ASM: mrs x8, PMEVCNTR30_EL0
54-
// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD8:.*]])
63+
// CHECK-ASM: mrs x0, PMEVCNTR30_EL0
64+
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD8:.*]])
65+
// CHECK-IR-NEXT: store i64 %[[VAR]]
5566

5667
ret = _ReadStatusReg(ARM64_TPIDR_EL0);
57-
// CHECK-ASM: mrs x8, TPIDR_EL0
58-
// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD9:.*]])
68+
// CHECK-ASM: mrs x0, TPIDR_EL0
69+
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD9:.*]])
70+
// CHECK-IR-NEXT: store i64 %[[VAR]]
5971

6072
ret = _ReadStatusReg(ARM64_TPIDRRO_EL0);
61-
// CHECK-ASM: mrs x8, TPIDRRO_EL0
62-
// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD10:.*]])
73+
// CHECK-ASM: mrs x0, TPIDRRO_EL0
74+
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD10:.*]])
75+
// CHECK-IR-NEXT: store i64 %[[VAR]]
6376

6477
ret = _ReadStatusReg(ARM64_TPIDR_EL1);
65-
// CHECK-ASM: mrs x8, TPIDR_EL1
66-
// CHECK-IR: call i64 @llvm.read_register.i64(metadata ![[MD11:.*]])
78+
// CHECK-ASM: mrs x0, TPIDR_EL1
79+
// CHECK-IR: %[[VAR:.*]] = call i64 @llvm.read_register.i64(metadata ![[MD11:.*]])
80+
// CHECK-IR-NEXT: store i64 %[[VAR]]
6781

6882

6983
_WriteStatusReg(ARM64_CNTVCT, v);
70-
// CHECK-ASM: msr S3_3_C14_C0_2, x8
71-
// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD2:.*]], i64 {{%.*}})
84+
// CHECK-ASM: msr S3_3_C14_C0_2, x0
85+
// CHECK-IR: %[[VAR:.*]] = load i64,
86+
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD2:.*]], i64 %[[VAR]])
7287

7388
_WriteStatusReg(ARM64_PMCCNTR_EL0, v);
74-
// CHECK-ASM: msr PMCCNTR_EL0, x8
75-
// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD3:.*]], i64 {{%.*}})
89+
// CHECK-ASM: msr PMCCNTR_EL0, x0
90+
// CHECK-IR: %[[VAR:.*]] = load i64,
91+
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD3:.*]], i64 %[[VAR]])
7692

7793
_WriteStatusReg(ARM64_PMSELR_EL0, v);
78-
// CHECK-ASM: msr PMSELR_EL0, x8
79-
// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD4:.*]], i64 {{%.*}})
94+
// CHECK-ASM: msr PMSELR_EL0, x0
95+
// CHECK-IR: %[[VAR:.*]] = load i64,
96+
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD4:.*]], i64 %[[VAR]])
8097

8198
_WriteStatusReg(ARM64_PMXEVCNTR_EL0, v);
82-
// CHECK-ASM: msr PMXEVCNTR_EL0, x8
83-
// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD5:.*]], i64 {{%.*}})
99+
// CHECK-ASM: msr PMXEVCNTR_EL0, x0
100+
// CHECK-IR: %[[VAR:.*]] = load i64,
101+
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD5:.*]], i64 %[[VAR]])
84102

85103
_WriteStatusReg(ARM64_PMXEVCNTRn_EL0(0), v);
86-
// CHECK-ASM: msr PMEVCNTR0_EL0, x8
87-
// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD6:.*]], i64 {{%.*}})
104+
// CHECK-ASM: msr PMEVCNTR0_EL0, x0
105+
// CHECK-IR: %[[VAR:.*]] = load i64,
106+
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD6:.*]], i64 %[[VAR]])
88107

89108
_WriteStatusReg(ARM64_PMXEVCNTRn_EL0(1), v);
90-
// CHECK-ASM: msr PMEVCNTR1_EL0, x8
91-
// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD7:.*]], i64 {{%.*}})
109+
// CHECK-ASM: msr PMEVCNTR1_EL0, x0
110+
// CHECK-IR: %[[VAR:.*]] = load i64,
111+
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD7:.*]], i64 %[[VAR]])
92112

93113
_WriteStatusReg(ARM64_PMXEVCNTRn_EL0(30), v);
94-
// CHECK-ASM: msr PMEVCNTR30_EL0, x8
95-
// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD8:.*]], i64 {{%.*}})
114+
// CHECK-ASM: msr PMEVCNTR30_EL0, x0
115+
// CHECK-IR: %[[VAR:.*]] = load i64,
116+
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD8:.*]], i64 %[[VAR]])
96117

97118
_WriteStatusReg(ARM64_TPIDR_EL0, v);
98-
// CHECK-ASM: msr TPIDR_EL0, x8
99-
// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD9:.*]], i64 {{%.*}})
119+
// CHECK-ASM: msr TPIDR_EL0, x0
120+
// CHECK-IR: %[[VAR:.*]] = load i64,
121+
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD9:.*]], i64 %[[VAR]])
100122

101123
_WriteStatusReg(ARM64_TPIDRRO_EL0, v);
102-
// CHECK-ASM: msr TPIDRRO_EL0, x8
103-
// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD10:.*]], i64 {{%.*}})
124+
// CHECK-ASM: msr TPIDRRO_EL0, x0
125+
// CHECK-IR: %[[VAR:.*]] = load i64,
126+
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD10:.*]], i64 %[[VAR]])
104127

105128
_WriteStatusReg(ARM64_TPIDR_EL1, v);
106-
// CHECK-ASM: msr TPIDR_EL1, x8
107-
// CHECK-IR: call void @llvm.write_register.i64(metadata ![[MD11:.*]], i64 {{%.*}})
129+
// CHECK-ASM: msr TPIDR_EL1, x0
130+
// CHECK-IR: %[[VAR:.*]] = load i64,
131+
// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD11:.*]], i64 %[[VAR]])
108132
}
109133

110134
// CHECK-IR: ![[MD2]] = !{!"3:3:14:0:2"}

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