@@ -4,9 +4,8 @@ use rustc_codegen_ssa::mir::operand::OperandValue;
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use rustc_codegen_ssa:: mir:: place:: PlaceRef ;
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use rustc_codegen_ssa:: traits:: { AsmBuilderMethods , AsmMethods , BaseTypeMethods , BuilderMethods , GlobalAsmOperandRef , InlineAsmOperandRef } ;
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- use rustc_hir:: LlvmInlineAsmInner ;
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use rustc_middle:: { bug, ty:: Instance } ;
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- use rustc_span:: { Span , Symbol } ;
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+ use rustc_span:: Span ;
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use rustc_target:: asm:: * ;
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use std:: borrow:: Cow ;
@@ -106,17 +105,6 @@ enum ConstraintOrRegister {
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impl < ' a , ' gcc , ' tcx > AsmBuilderMethods < ' tcx > for Builder < ' a , ' gcc , ' tcx > {
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- fn codegen_llvm_inline_asm ( & mut self , _ia : & LlvmInlineAsmInner , _outputs : Vec < PlaceRef < ' tcx , RValue < ' gcc > > > , _inputs : Vec < RValue < ' gcc > > , span : Span ) -> bool {
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- self . sess ( ) . struct_span_err ( span, "GCC backend does not support `llvm_asm!`" )
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- . help ( "consider using the `asm!` macro instead" )
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- . emit ( ) ;
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-
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- // We return `true` even if we've failed to generate the asm
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- // because we want to suppress the "malformed inline assembly" error
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- // generated by the frontend.
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- true
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- }
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-
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fn codegen_inline_asm ( & mut self , template : & [ InlineAsmTemplatePiece ] , rust_operands : & [ InlineAsmOperandRef < ' tcx , Self > ] , options : InlineAsmOptions , span : & [ Span ] , _instance : Instance < ' _ > , _dest_catch_funclet : Option < ( Self :: BasicBlock , Self :: BasicBlock , Option < & Self :: Funclet > ) > ) {
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if options. contains ( InlineAsmOptions :: MAY_UNWIND ) {
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self . sess ( )
@@ -184,7 +172,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> {
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let is_target_supported = reg. reg_class ( ) . supported_types ( asm_arch) . iter ( )
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. any ( |& ( _, feature) | {
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if let Some ( feature) = feature {
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- self . tcx . sess . target_features . contains ( & Symbol :: intern ( feature) )
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+ self . tcx . sess . target_features . contains ( & feature)
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} else {
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true // Register class is unconditionally supported
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}
@@ -572,6 +560,7 @@ fn reg_to_gcc(reg: InlineAsmRegOrRegClass) -> ConstraintOrRegister {
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InlineAsmRegClass :: Hexagon ( HexagonInlineAsmRegClass :: reg) => unimplemented ! ( ) ,
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InlineAsmRegClass :: Mips ( MipsInlineAsmRegClass :: reg) => unimplemented ! ( ) ,
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InlineAsmRegClass :: Mips ( MipsInlineAsmRegClass :: freg) => unimplemented ! ( ) ,
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+ InlineAsmRegClass :: Msp430 ( _) => unimplemented ! ( ) ,
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InlineAsmRegClass :: Nvptx ( NvptxInlineAsmRegClass :: reg16) => unimplemented ! ( ) ,
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InlineAsmRegClass :: Nvptx ( NvptxInlineAsmRegClass :: reg32) => unimplemented ! ( ) ,
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InlineAsmRegClass :: Nvptx ( NvptxInlineAsmRegClass :: reg64) => unimplemented ! ( ) ,
@@ -634,6 +623,7 @@ fn dummy_output_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, reg: InlineAsmRegCl
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InlineAsmRegClass :: Hexagon ( HexagonInlineAsmRegClass :: reg) => cx. type_i32 ( ) ,
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InlineAsmRegClass :: Mips ( MipsInlineAsmRegClass :: reg) => cx. type_i32 ( ) ,
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InlineAsmRegClass :: Mips ( MipsInlineAsmRegClass :: freg) => cx. type_f32 ( ) ,
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+ InlineAsmRegClass :: Msp430 ( _) => unimplemented ! ( ) ,
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InlineAsmRegClass :: Nvptx ( NvptxInlineAsmRegClass :: reg16) => cx. type_i16 ( ) ,
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InlineAsmRegClass :: Nvptx ( NvptxInlineAsmRegClass :: reg32) => cx. type_i32 ( ) ,
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InlineAsmRegClass :: Nvptx ( NvptxInlineAsmRegClass :: reg64) => cx. type_i64 ( ) ,
@@ -741,6 +731,7 @@ fn modifier_to_gcc(arch: InlineAsmArch, reg: InlineAsmRegClass, modifier: Option
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InlineAsmRegClass :: Bpf ( _) => unimplemented ! ( ) ,
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InlineAsmRegClass :: Hexagon ( _) => unimplemented ! ( ) ,
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InlineAsmRegClass :: Mips ( _) => unimplemented ! ( ) ,
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+ InlineAsmRegClass :: Msp430 ( _) => unimplemented ! ( ) ,
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InlineAsmRegClass :: Nvptx ( _) => unimplemented ! ( ) ,
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InlineAsmRegClass :: PowerPC ( _) => unimplemented ! ( ) ,
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InlineAsmRegClass :: RiscV ( RiscVInlineAsmRegClass :: reg)
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